Native Read Timing

1. Master asserts read enable signal with valid address and wait for the read acknowledgement from the SDRAM controller.
2. SDRAM controller acknowledges to the read enable
3. Master updates the next address. Read enable signal remains high for a burst read.
4. Master terminates the burst read by asserting the last signal.
5. Master de-asserts read enable and last signals.
6. SDRAM controller asserts read valid signal to indicate that the data is ready for master to read.
7. SDRAM controller continue to assert read valid signal until all read are sent out.