Customizing the SDRAM Controller

The core has parameters so you can customize its function. You set the parameters in the General tab of the core's IP Configuration window.

Table 1. SDRAM Controller Core Parameters
Parameters Options Description
Memory Clock Frequency 133, 166, 200 Define the SDRAM clock frequency, i_sdrclk in MHz.
Default = 200
I/O Round Trip Time >= 0 Define the I/O round trip time in controller clock cycles. Calibrate this parameter manually once per system.
Refer to Calibrate SDRAM Controller for steps to perform manual calibration.
Default = 2
CAS Latency 2, 3 Define the CAS latency in SDRAM clock cycles.
Default = 3
DDIO Register Implementation SOFT, HARD Select the double data rate I/O register implementation between:
  • Soft DDIO—implement with flip-flops
  • Hard DDIO—implement with I/O register
Default = SOFT
Data Bus Grouping 1, 2, 4 Define the data bus grouping per device.
Example:
  • A x32 width from four x8 devices
    dq_width = 8
    dq_group = 4
  • A x16 width from two x8 devices
    dq_width = 8
    dq_group = 2
Default = 4
Row Addressing Width 12, 13 Define the row addressing width.
Default = 13
Column Addressing Width 8, 9, 10 Define the column addressing width.
Default = 10
tPWRUP (ns) 100000, 200000 Define the power-up sequence in ns.
Default = 200000
Minimum tRAS (ns) 37, 40, 42, 44 Define the minimum time for ACTIVE-to-PRECHARGE command in ns.
This value must be higher than the minimum tRAS value stated in your SDRAM specification sheet.
Default = 44
Maximum tRAS (ns) 100000, 120000 Define the maximum time for ACTIVE-to-PRECHARGE command in ns.
This value must be lower than the maximum tRAS value stated in your SDRAM specification sheet.
Default = 120000
tRC (ns) 55, 60, 63, 66 Define the ACTIVE-to-ACTIVE command period in ns.
This value must be higher than the minimum tRC value stated in your SDRAM specification sheet.
Default = 66
tRCD (ns) 15, 18, 20 Define the ACTIVE-to-READ or WRITE delay in ns.
This value must be higher than the minimum tRCD value stated in your SDRAM specification sheet.
Default = 20
tREF (ns) 25000000 – 64000000 Define the refresh period in ns.
This value must be lower than the maximum tREF value stated in your SDRAM specification sheet.
Default = 64000000
tRFC (ns) 55, 66 Define the AUTO REFRESH period in ns.
This value must be higher than the minimum tRFC value stated in your SDRAM specification sheet.
Default = 66
tRP (ns) 15, 18, 20 Define the PRECHARGE command period in ns.
This value must be higher than the minimum tRP value stated in your SDRAM specification sheet.
Default = 20
Controller Interface AXI4, Native Defines the user interface.
Default = AXI4
Data Rate Half rate, Full rate Defines the fsys_mhz. Data rate = fck_mhz / fsys_mhz.
Default = Half rate

The SDRAM Controller core has pre-defined parameters that are not included in the IP Configuration window. These parameters cannot be changed and listed below as reference.

Table 2. SDRAM Controller Pre-Defined Parameters
Parameters Options Description
Burst length 1 Burst length.
Memory Data Width 8
Data input/output bus width per device.
Used with the dq_group parameter.
Bank Addressing Width 2 Bank addressing width.
tWR 2
Define the WRITE recovery time in ns.
This value must be higher than the minimum tWR value stated in your SDRAM specification sheet.
tMRD 2
Define the LOAD MODE REGISTER command to ACTIVE or REFRESH command in SDRAM clock cycles.
This value must comply with the tWR value stated in your SDRAM specification sheet.