Revision History
| Date | Document Version | IP Version | Description |
|---|---|---|---|
| December 2024 | 2.1 | 5.13 | Changed Optional Signals to Example Design Deliverables Option in DDR3 Soft Controller Example Design and Testbench Deliverables Option in DDR3 Soft Controller Testbench. (DOC-2276) |
| November 2024 | 2.0 | 5.13 | Updated IP Version in Revision History. (DOC-2185) |
| November 2024 | 1.9 | 5.14 | Added Topaz in Device Support. (DOC-2126) Added IP Version in
Revision History. (DOC-2185) |
| June 2024 | 1.8 | – | Updated topic Read Enable Pipeline to Auto Read Enable Pipeline.
(DOC-1924) Removed Read Enable Pipeline parameter in Parameters
(General Tab) of Customizing the DDR3 Soft Controller
topic. Added important note in Example Design and
Testbench regarding using default parameters options only.
(DOC-1781) |
| December 2023 | 1.7 | – | Updated Column, Row, and IP Manager parameters. Corrected AXI
interface block diagram signals. (DOC-1563) Updated Attaching
FMC DDR3 and GPIO Daughter Card.
(DOC-1568) Updated Testbench files. |
| October 2023 | 1.6 | – |
Corrected shift, shift_sel, and shift_ena signal widths in the
block diagram. (DOC-1509)
|
| June 2023 | 1.5 | – |
Added Device Support and release notes sections. (DOC-1234)
|
| May 2023 | 1.4 | – | Added Read Enable Pipeline section. (DOC-1241) |
| February 2023 | 1.3 | – | Updated for Efinity IP Manager support. Added
note about The resource and performance values in the resource and
utilization table are for guidance only. |
| October 2022 | 1.2 | – | Added READ_ENABLE_PIPELINE parameter. |
| July 2022 | 1.1 | – | Added support for Titanium Ti180 FPGA and AXI4 interface. |
| March 2022 | 1.0 | – | Initial release. |