Arbiter

The DDR3 Soft Controller core includes an arbiter that manages the priority for write and read operations. The arbiter also controls the number of consecutive read or write operations before switching to another read or write operation.

The following waveforms illustrates the examples of read and write operation based on predefined arbiter parameters.

Figure 1. arbiter_init = 0, arbiter_count = 4 Example Waveform

Figure 2. arbiter_init = 1, arbiter_count = 1 Example Waveform

Figure 3. arbiter_init = 1, arbiter_count = 1 Example Waveform (with Write Buffer Empty)

Figure 4. arbiter_init = 0, arbiter_count = 8 Example Waveform (with Write Buffer Empty and Read Buffer Empty)