Functional Description

The DDR3 Soft Controller core consists of the following blocks:

Instruction RAM—Instruction memory for the main controller behavior
Main Controller—Main state machine of the DDR3 controller
Arbiter—Handles the write and read prioritization
Buffer—64 depth buffer for write and read data
Input Auto-Calibration—For DQ input clock (tac_clock) calibration

Figure 1. DDR3 Soft Controller Native Block Diagram

Figure 2. DDR3 Soft Controller with AXI4 Interface Block Diagram