Ports

Table 1. Clocks
Port Direction Description
clk Input Controller clock for user interface.
core_clk Input Main controller (state machine) clock frequency.
tdqss_clk Input Output clock for DDR's address, control and DQS signals. Same as PHY clock frequency.
twd_clk Input DQ/DM output write clock. Same as PHY clock frequency.
tac_clk Input DQ/DQS input read clock. Same as PHY clock frequency.

Table 2. User Interface
m = DRAM_WIDTH*BL
n = GROUP_WIDTH/8*BL
Port Direction Description
wr_data[m-1:0] Input Data to be written to DRAM.
wr_datamask[n-1:0] Input Datamask to be written to DRAM.
wr_addr[31:0] Input Write address (byte) to DRAM in [ROW, BANK, COL].
wr_addr_en Input Enable to write wr_addr.
wr_en Input Write data with wr_data and wr_datamask.
rd_addr[31:0] Input Read address (byte) to DRAM in [ROW, BANK, COL].
rd_addr_en Input Enable to read rd_addr.
rd_en Input Ready for read.
reset_n Input Active low reset for the controller.
wr_busy Output Busy status of the write buffer is full. The core cannot perform a write operation when this signal is asserted.
wr_ack Output Write acknowledge. Handshaking with write enable(wr_en).
rd_busy Output Busy status of the read buffer is full. The core cannot perform a read operation when this signal is asserted.
rd_data[m-1:0] Output Data read from DRAM. o_rd_data shares the same data address mapping as wr_data.
rd_valid Output Read valid. The data on o_rd_valid is valid to be read.
rd_ack Output Read acknowledge. Handshaking with read address enable (rd_addr_en).
shift[2:0] Output PLL auto-calibration value.1
shift_sel[4:0] Output Selects the clock for PLL auto-calibration for PLL (tac_clk only).1
shift_ena Output PLL auto-calibration for PLL enabled.1
cal_ena Input Assert this signal to enable the auto-calibration function.
cal_done Output Auto-calibration function done.1
cal_pass Output Logic high indicates the auto-calibration function passed.
cal_fail_log[6:0] Output Logic high indicates the calibration result of phase shift failed.
Bit[6]: Phase shift value 6 PASS:0 FAIL:1
Bit[5]: Phase shift value 5 PASS:0 FAIL:1
Bit[4]: Phase shift value 4 PASS:0 FAIL:1
Bit[3]: Phase shift value 3 PASS:0 FAIL:1
Bit[2]: Phase shift value 2 PASS:0 FAIL:1
Bit[1]: Phase shift value 1 PASS:0 FAIL:1
Bit[0]: Phase shift value 0 PASS:0 FAIL:1
cal_shift_val[2:0] Output Current phase shift value after calibration.
Table 3. AXI4 Interface
p = WFIFO_WIDTH
Port Direction Description
axi_aid[7:0] Input Read or write address channel transaction ID
axi_aaddr[31:0] Input Read or write address channel address.
axi_alen[7:0] Input Read or write address channel burst length.
axi_asize[2:0] Input Read or write address channel transfer size.
axi_aburst[1:0] Input Read or write address channel burst type.
axi_alock[1:0] Input Read or write address channel locked transaction.
axi_avalid Input Read or write address channel valid
axi_atype Input 0: Change all axi_ax signals for read address channel
1: Change all axi_ax signals for write address channel
axi_wid[7:0] Input Write channel transaction ID
axi_wdata[p-1:0] Input Write channel data
axi_wstrb[15:0] Input Write channel strobe (Single bit represents data byte)
axi_wlast Input Write channel last data
axi_wvalid Input Write channel valid
axi_rready Input Read data channel ready
axi_bready Input Write response channel ready
axi_aready Output Read or write address channel ready
axi_wready Output Write channel ready
axi_rid[7:0] Output Read data channel transaction ID
axi_rdata[p-1:0] Output Read data channel data
axi_rlast Output Read data channel last data
axi_rvalid Output Read data channel valid
axi_rresp[1:0] Output Read data channel response
axi_bid[7:0] Output Write response channel transaction ID
axi_bvalid Output Write response channel valid
axi_bresp[1:0] Output Write response channel response
Table 4. DDR Interface
q = DRAM_WIDTH
r = DRAM_GROUP
Port Direct Clock Domain Description
phy_ddr_dq_IN_HI[q-1:0] Input tac_clk DDR3 DQ input for DDIO HI.
phy_ddr_dq_IN_LO[q-1:0] Input tac_clk DDR3 DQ input for DDIO LO.
phy_ddr_dqs_n_IN_HI[r-1:0] Input tac_clk DDR3 DQS# input for DDIO HI.
phy_ddr_dqs_n_IN_LO[r-1:0] Input tac_clk DDR3 DQS# input for DDIO LO.
phy_ddr_dqs_p_IN_HI[r-1:0] Input tac_clk DDR3 DQS input for DDIO HI.
phy_ddr_dqs_p_IN_LO[r-1:0] Input tac_clk DDR3 DQS input for DDIO LO.
phy_ddr_addr[15:0] Output tdqss_clk DDR3 A[15:0].
phy_ddr_ba[2:0] Output tdqss_clk DDR3 BA[2:0].
phy_ddr_cas Output tdqss_clk DDR3 CAS#.
phy_ddr_cke Output tdqss_clk DDR3 CKE.
phy_ddr_cs Output tdqss_clk DDR3 CS#.
phy_ddr_dm_OUT_HI[r-1:0] Output twd_clk DDR3 DM for DDIO HI.
phy_ddr_dm_OUT_LO[r-1:0] Output twd_clk DDR3 DM for DDIO LO.
phy_ddr_dq_OE[q-1:0] Output twd_clk DDR3 DQ output enable.
phy_ddr_dq_OUT_HI[q-1:0] Output twd_clk DDR3 DQ output for DDIO HI.
phy_ddr_dq_OUT_LO[q-1:0] Output twd_clk DDR3 DQ output for DDIO LO.
phy_ddr_dqs_n_OE[r-1:0] Output tdqss_clk DDR3 DQS# output enable.
phy_ddr_dqs_n_OUT_HI[r-1:0] Output tdqss_clk DDR3 DQS# output for DDIO HI.
phy_ddr_dqs_n_OUT_LO[r-1:0] Output tdqss_clk DDR3 DQS# output for DDIO LO.
phy_ddr_dqs_p_OE[r-1:0] Output tdqss_clk DDR3 DQS output enable.
phy_ddr_dqs_p_OUT_HI[r-1:0] Output tdqss_clk DDR3 DQS output for DDIO HI.
phy_ddr_dqs_p_OUT_LO[r-1:0] Output tdqss_clk DDR3 DQS output for DDIO LO.
phy_ddr_odt Output tdqss_clk DDR3 ODT.
phy_ddr_ras Output tdqss_clk DDR3 RAS#.
phy_ddr_rstn Output tdqss_clk DDR3 RESET#.
phy_ddr_we Output tdqss_clk DDR3 WE#.
1 Connect this signal to PLL in the Interface Designer if you are using the auto-calibration function.