Interface Designer Settings

When creating your own DDR3 Soft Controller core design, you need to create GPIO blocks/buses and PLL output clocks in the Efinity Interface Designer with the settings shown in following tables.

Table 1. Interface Designer Settings for PLL
Option Output Clock 0 Output Clock 1 Output Clock 2 Output Clock 3 Output Clock 4
Instance Name tdqss_clk core_clk tac_clk twd_clk Feedback clk
Clock Frequency (MHz) 400 200 400 400 50
Phase Shift 0 0 Dynamic 90 0
Table 2. Interface Designer Settings for GPIO
Block/Bus Settings
Mode I/O standard Register Option Double Data I/O Option Clock Inverted Clock
clk_p clkout 1.5 V Differential SSTL - - tdqss_clk Yes
cke output 1.5 V SSTL register - tdqss_clk -
Addr[15:0] output 1.5 V SSTL register - tdqss_clk -
Ba[2:0] output 1.5 V SSTL register - tdqss_clk -
cs output 1.5 V SSTL register - tdqss_clk -
ras output 1.5 V SSTL register - tdqss_clk -
cas output 1.5 V SSTL register - tdqss_clk -
we output 1.5 V SSTL register - tdqss_clk -
i_dq_hi[15:0 input 1.5 V SSTL register resync tac_clk -
i_dq_lo[15:0] input 1.5 V SSTL register resync tac_clk -
o_dq_hi[15:0] output 1.5 V SSTL register resync twd_clk -
o_dq_lo [15:0] output 1.5 V SSTL register resync twd_clk -
o_dq_oe[15:0] output 1.5 V SSTL register - twd_clk -
i_dqs_hi input 1.5 V Differential SSTL register resync tac_clk -
i_dqs_lo input 1.5 V Differential SSTL register resync tac_clk -
o_dqs_hi output 1.5 V Differential SSTL register resync tdqss_clk -
o_dqs_lo output 1.5 V Differential SSTL register resync tdqss_clk -
o_dqs_oe output 1.5 V Differential SSTL register - tdqss_clk -
o_dqs_n_oe output 1.5 V Differential SSTL register - tdqss_clk -
o_dm_hi output 1.5 V SSTL register resync twd_clk -
o_dm_lo output 1.5 V SSTL register resync twd_clk -
odt output 1.5 V SSTL register - tdqss_clk -
reset output 1.5 V SSTL register - tdqss_clk -