Resource Utilization and Performance

Note: The resources and performance values provided are based on some of the supported FPGAs. These values are just guidance and may change depending on the device resource utilization, design congestion, and user design.
Table 2. Titanium Resource Utilization and PerformanceUsing TIMING_2 optimization in Efinity®'s Place-and-Route.
FPGA Mode Logic and Adders Flip-flops Memory Blocks Efinity® Version
Ti180 J484 C4 AXI4 2,278 2,017 27 2023.2
Native 1,840 1,726 27 2023.2
1 Using Verilog HDL.