Operation Examples

The following waveforms illustrate examples of write and read operations.

The write operation starts when you assert the wr_en signal high. The write operation stops when the wr_en signal is de-asserted. The DDR3 Soft Controller core asserts the wr_ack signal when the data is successfully written into the DDR3 memory.

Figure 1. Write Operation Example Waveform

The read operation starts when you assert the rd_en signal. The DDR3 Soft Controller core asserts the rd_ack to acknowledge that a read operation at the specified address is received. The read data is available at the rd_data port when the rd_valid is asserted.

Figure 2. Read Operation Example Waveform

Auto Read Enable Pipeline

The Read Enable Pipeline parameter is an additional pipeline on top of the memory Read Latency parameter settings. This parameter is to account for:
  • Board trace delays
  • DDIO delays
  • Finding the word boundary to start de-serializing the incoming read data. For example, for a x16 DRAM, the data is de-serialized to AXI data width of 128 bits.

The core will automatically set the correct parameter.