DDR3 Soft Controller Example Design

You can choose to generate the example design when generating the core in the IP Manager Configuration window. Compile the example design project and download the .hex or .bit file to your board. To generate example design, the Example Design Deliverables Option signal must be enabled.

Important: tested the example design generated with the default parameter options only.

The example design targets the Titanium Ti180 J484 Development Board with the FMC DDR3 and GPIO Daughter Card attached. The IP Manager generates the native or AXI4 mode example design depending on the DDR Interface parameter you select.

Figure 1. Example Design Block Diagram
The design performs calibration, write, read, and compares the write and read operations (memory checking). The design then outputs the operation results through the Titanium Ti180 J484 Development Board LEDs.
Table 1. Example Design LEDs
LED Description
LED2 DDR3 memory calibration done
LED3 DDR3 memory calibration pass
LED4 DDR3 memory checker done
LED5 DDR3 memory checker pass
Table 2. Example Design Implementation
FPGA Mode Logic and Adders Flip-flops Memory Blocks fMAX Efinity® Version1
Ti180 J484 C4 AXI4 2,564 2,143 27 2 2023.2
Native 2,923 2,000 27 2023.2
1 Using Verilog HDL.
2 Clock out fMAX matched the PLL settings in Table 1.