Revision History

Added i2c_writeData_b_ack(), i2c_writeData_w_ack(), i2c_readData_b_ack(), i2c_readData_w_ack() in I2C API Calls. Updated i2c_writeData_w().

Added chapter Concurrent Debug chapter.

Change AXI master/slave interface 0/1.

Updated typo at Modify the Bootloader Software to extend the External Memory Size, Create a Custom APB3 Peripheral, Application Software in Migrating to Sapphire SoC, Memory Test of Troubleshooting. Corrected name in step 5 of Target another Efinix Voard. (DOC-2769)

Added new troubleshooting topics in Troubleshooting chapter.

Updated table List of Files Structure Changes and added table List of Reallocation File in List of Restructured BSP Files.

Added note in Table 13.

Updated Modify the Bootloader Software to Enable Multi-Data Lines.

Included Topaz Tz170 J484 into About the Example Design.

Added sub-topic IDE Launcher from Efinity.

Added note in Create a New Project and Import Sample Projects.

Added directory in table BSP Files.

Added subtopic List of Restructured BSP Files.

In Example Software, removed compatibilityDemo, freertosUartInterruptDemo, openocdServer, spiReadFlash, and spiWriteFlash, and freertosDemo2 in FreeRTOS. Replaced coreTimerInterrupt Demo with clintTimerInterruptDemo. Updated content for dCacheFlushDemo, spiDemo, Download the FreeRTOS.

Removed note in chapter Create, Import, and Build a Software Project.

Added Watchdog Timer chapter.

Added in option 32 for GPIO n Bit Width in table Sapphire GPIO Tab Parameters.

Updated Simulate chapter.

Updated Create a New Project and Import Sample Projects topic.

Added semihostngDemo in Example Software.

Added in Semihosting Printing section in Unified Printf.

Added ENABLE_SEMIHOSTING_PRINT in Preprocessor Directives.

Added new example software inlineASMDemo.

Added new topic Inline Assembly.

Corrected wording of images with prints/messages in software examples. (DOC-1419)

–Control and Status Registers

–GPIO API Calls

–I²C API Calls

–Core Local Interrupt Timer API Calls

–User Timer API Calls

–PLIC API Calls

–SPI API Calls

–SPI Flash Memory API Calls

–UART API Calls

–RISC-V API Calls (new)

Added footnote in Sapphire Debug Tab Parameters table.

Added new section: Launching OpenOCD for Your Own Board and Updating OpenOCD Configuration for External FTDI Cable in Target Your Own Board topic.

Added new topic: Updating Bootloader with Efinity BRAM Initial Content Updater under Modify the Bootloader topic.

Added new section: i2cMasterDemo Design.

Replaced new content in i2cSlaveDemo Design section.

Replaced the section Warning when Debug with softTap with Unexpected CPUTAPID/JTAG Device ID.

Added new paragraph after Default Address Map, Interrupt ID, and Cached Channels table in Address Map topic. (DOC-1199)

Updated the following sections: (DOC-1253)

–Customizing the Sapphire SoC

–Example Design Implementation table

–Launch the Debug Script

–Debug Daisy Chain

–Example Software

–API Reference

Added new topic: Other Customize Debugger

Added in new sub-topics:

–Debug - Single Core and Debug - SMP

–dCacheFlushDemo, iCacheFlushDemo, and 12CEepromDemo

–i2C_getSlaveStatus(), i2C_getSlaveOverride(), and i2C_masterRecoverBlocking()

Change Ti180M484 to Ti180J484.

Changed topic title, Connect the FTDI Cable → Connect the FTDI Mini-Module and FTDI cable → FTDI mini-module

Added new main topics:

–Launch Efinity RISC-V Embedded Software IDE

–Create and Build a Software Project

–Debug with the OpenOCD Debugger

–Unified Printf

Added new sub-topics:

–Efinity RISC-V Embedded Software IDE

–Install the Efinity RISC-V Embedded Software IDE

–SoC Configuration Guideline

–Sapphire SoC IDE Backward Compatibility

–Launching the Efinity RISC-V Embedded Software IDE.

–Optimization Settings

–Import Sample Projects

–Debug - Daisy Chain

–Peripheral Register View

–CSR Register View

–FreeRTOS View

–QEMU Emulator

–Bsp_print

–Bsp_printf

–Bsp_printf_full

–Preprocessor Directives

–Warning when Debug with softTap

Updated on sub-topics Open a Terminal, Connect the FTDI Cable, OpenOCD Error: timed out while waiting for target halted, Memory Test, Eclipse Fails to Launch with Exit Code 13, and API Reference.

Updated Appendix: Copy a User Binary to the Flash Device (2 Terminals) and Import the Debug Configuration.

Updated the instructions for debugging with OpenOCD. You now use launch scripts.

Added information on the possible boot sequence scenarios.

Enhanced the information on the address map.

Added description for debugging with multiple cores.

Added new SPI API functions.

Added instructions on migrating from Ruby, Jade, and Opal to Sapphire.

Updated IP Manager configuration options.

Updated instructions on launching Eclipse.

Updated Installing USB drivers topics.

The VexRiscv core used in the Sapphire SoC has six pipeline stages.

Updated the IP Manager Configuration Wizard description for new configuration options.

Added instructions for using the Ti60 F225 Development Board and example design.

Updated instructions for Eclipse global environment variables.

Explained new Efinity Programmer feature for programming a flash device with a combined user bitstream and application binary.

Updated register map.

Updated the API Reference for new driver support.

IP Manager options changed for the updated Sapphire wizard. (DOC-544)

Updated the address map. (DOC-544)

Updated the example design description for the new features in the design. (DOC-544)

New simulation instructions. (DOC-544)

New instructions for changing the bootloader RAM size. (DOC-544)

Changed the TX pin number for the instructions on setting up a USB-to-UART module. (DOC-544)

When using the Soft Debug Tap option, the IP Manager connects the pins for you. (DOC-544)

Described the pins needed to connect an FTDI cable to the Trion® T120 BGA324 Development Board when using the Soft Debug Tap option. (DOC-544)