Trion FPGA Overview
The Efinix® Trion® programmable platform, built on Efinix Quantum™ technology, delivers substantial Power-Performance-Area advantages over traditional FPGA products. Trion FPGAs feature programmable logic and a routing fabric built using Quantum technology. The fabric is wrapped with an I/O interface in a small footprint package that is required by many high-volume applications such as mobile and IoT. In addition to logic and routing, the fabric includes embedded memory blocks and multiplier blocks (or DSP blocks).
The initial phase of the Trion platform is built on SMIC's 40LL process, with a logic density range from 4K to 120K logic elements (LEs) and standard interfaces such as GPIO, PLLs, oscillators, MIPI, DDR, LVDS, etc. Trion FPGAs target general-purpose custom logic markets (mobile, IoT, general consumer, industrial, and medical) as well as fast-growing markets such as compute acceleration and deep learning in edge devices.
Trion FPGA Block Diagram
Resource and Packaging Overview
Resources and Interfaces
|Logic Elements (LEs)||3,888||7,384||12,828||19,728||31,680||54,195||84,096||112, 128|
|Embedded RAM Bits (kb)||77||123||727||1,044||1,475||2,765||4,055||5,407|
|Maximum GPIO (1)||55||97||195||222||222||278||278||278|
|LVDS (TX, RX)||—||6, 6||13, 13||20, 26||20, 26||52, 52||52, 52||52, 52|
|DDR3, LPDDR3, LPDDR2
|MIPI 4-lane DPHY with
built-in CSI-2 controller
|49-ball FBGA (0.4 mm, 3x3 mm)|
|81-ball FBGA (0.5 mm, 5x5 mm)|
|144-pin LQFP (0.5 mm, 20x20 mm)
|169-ball FBGA (0.65 mm, 9x9 mm)
|256-ball FBGA (0.8 mm, 13x13 mm)|
|324-ball FBGA (0.65 mm, 12x12 mm)|
|400-ball FBGA (0.8 mm, 16x16 mm)|
|484-ball FBGA (0.8 mm, 18x18 mm))|
|576-ball FBGA (0.65 mm, 16x16 mm)|
|676-ball FBGA (0.8 mm, 21x21 mm)|
Standard I/O Interfaces
The initial rollout of Trion FPGAs supports the following interfaces:
- MIPI—4-lane MIPI D-PHY with a built-in (hardened) CSI-2 controller and up to 6 Gbps per PHY. Achieves low power and low cost, and provides a royalty-free, easy implementation for MIPI CSI-2.
- LVDS—Up to 800 Mbps LVDS data rate with up to 41.6 Gbps aggregate bandwidth.
- DDR—Provides DDR3, LPDDR3, LPDDR2 support. Up to 800 Mbps DDR line rates with up to 51.2 Gbps peak bandwidth. DDR Interface includes hardened PHY and memory controller, providing low power, low cost, and and easy to integrate memory interface.
Mask Programmable Memory (MPM)
The T4, T8, T13, and T20 FPGAs are equipped with optional MPM. With this feature, you use on-chip MPM instead of an external serial flash device to configure the FPGA. This option is for systems that require an ultra-small form factor and the lowest cost structure such that an external serial flash device is undesirable and/or not required at volume production. MPM is a one-time factory programmable option that requires a Non-Recurring Engineering (NRE) payment. To enable MPM, you submit your design to our factory; our Applications Engineers (AEs) convert your design into a single configuration mask to be specially fabricated.
Efinity Software Support
The Efinity® software provides a complete tool flow from RTL design to bitstream generation, including synthesis, place-and-route, and timing analysis. The software has a graphical user interface (GUI) that provides a visual way to set up projects, run the tool flow, and view results. The software also has a command-line flow and Tcl command console. The software-generated bitstream file configures Trion devices. The software supports the Verilog HDL and VHDL languages. Read more