L2 Cache Controller (L2CTRL) driver.
This module provides functions to configure and control L2CTRL input/output and interrupt behavior.
Usage & Initialization.
This example shows how to flush L2 Cache using Blocking Method .
void main()
{
char buf[40];
u64 *dat = (
u64 *)SYSTEM_AXI_B_CTRL;
for(int i=0; i < (4096/sizeof(uintptr_t)); i=i+1) {
*dat = (0x0101010101010101*i);
dat++;
}
dat--;
for(int i=0; i < (4096/sizeof(uintptr_t)); i=i+1) {
val=*dat;
dat--;
}
printf("Flush done ..\n");
}
void l2cache_flushBlocking(void *address, u64 size)
Use the L2 cache registers to flush a range of memory, using physical address and wait until the flus...
L2 controller driver API definitions.
This example shows how to flush L2 Cache using Interrupt Method .
printf("isr: Flush done ..\n");
asm("fence");
return 0;
}
void l2_isr_init() {
.gateway = SYSTEM_L2_CACHE_CTRL_INTERRUPT,
.priority = 0x1U,
.enable = 0X1U,
.threshold = 0x0U,
};
}
void main()
{
char buf[40];
u64 *dat = (
u64 *)SYSTEM_AXI_B_CTRL;
dat++;
for(int i=0; i < (4096/sizeof(uintptr_t)); i=i+1) {
*dat = (0x1010101010101010*i);
dat++;
}
dat--;
for(int i=0; i < (4096/sizeof(uintptr_t)); i=i+1) {
val=*dat;
dat--;
}
dat++;
while(1){};
}
#define BSP_PLIC_CPU_0
Primary PLIC CPU 0 External Interrupt base address.
void trap_entry(void)
The Main Trap Entry Point (Naked).
void irq_enable(void)
Enable Global Interrupts (MIE bit).
void irq_setType(cpu_irq_t enable)
Enable specific CPU interrupt sources.
void irq_setTrapVector(void(*trap_vector)(void))
Set the Machine Trap Vector (mtvec).
void l2cache_flush(void *address, u64 size)
Use the L2 cache registers to flush a range of memory, using physical address.
void l2cache_setFlushInterrupt(u64 mask)
Set L2 Cache Flush Interrupt.
void plic_applyConfig(plic_instance_t *inst)
Apply stored PLIC configuration to hardware.
RISC-V Core Interrupt Handling and Vector Table.
int irq_m_l2Cache_handler(void)
PLIC instance. Holds the software registers and hardware pointer.
- See also
- Example AXI-B Demo with L2 Cache - Learn how to use the driver with AXI-B Interface