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L2 Cache Controller Driver

Overview

L2 Cache Controller (L2CTRL) driver.

This module provides functions to configure and control L2CTRL input/output and interrupt behavior.

Usage & Initialization.

This example shows how to flush L2 Cache using Blocking Method .

#include "l2ctrl/l2ctrl.h"
void main()
{
char buf[40];
u64 val;
u64 *dat = (u64 *)SYSTEM_AXI_B_CTRL;
// Write 4KB data to axiB block ram
for(int i=0; i < (4096/sizeof(uintptr_t)); i=i+1) {
*dat = (0x0101010101010101*i);
dat++;
}
dat--;
// Read 4KB data from axiB block ram
for(int i=0; i < (4096/sizeof(uintptr_t)); i=i+1) {
val=*dat;
dat--;
}
// Data is now only available in L2 cache
// Flush the data to axiB block ram using blocking method
printf("Flush done ..\n");
}
void l2cache_flushBlocking(void *address, u64 size)
Use the L2 cache registers to flush a range of memory, using physical address and wait until the flus...
Definition l2ctrl.c:22
L2 controller driver API definitions.
uint64_t u64
Definition type.h:24

This example shows how to flush L2 Cache using Interrupt Method .

#include "l2ctrl/l2ctrl.h"
#include "irq.h"
// Interrupt handler for L2 Cache Flush completion
printf("isr: Flush done ..\n");
asm("fence");
return 0;
}
void l2_isr_init() {
plic_instance_t l2_plic = {
.target = BSP_PLIC_CPU_0,
.gateway = SYSTEM_L2_CACHE_CTRL_INTERRUPT,
.priority = 0x1U,
.enable = 0X1U,
.threshold = 0x0U,
};
plic_applyConfig(&l2_plic);
}
void main()
{
char buf[40];
u64 val;
u64 *dat = (u64 *)SYSTEM_AXI_B_CTRL;
dat++;
// Write another 4KB data to axiB block ram
for(int i=0; i < (4096/sizeof(uintptr_t)); i=i+1) {
*dat = (0x1010101010101010*i);
dat++;
}
dat--;
// Read 4KB data from axiB block ram
for(int i=0; i < (4096/sizeof(uintptr_t)); i=i+1) {
val=*dat;
dat--;
}
dat++;
// Flush the data to axiB block ram using nonblocking method and interrupt
l2cache_flush(dat, 4096);
while(1){};
}
#define BSP_PLIC_CPU_0
Primary PLIC CPU 0 External Interrupt base address.
Definition bsp.h:51
void trap_entry(void)
The Main Trap Entry Point (Naked).
Definition mtrap.c:129
void irq_enable(void)
Enable Global Interrupts (MIE bit).
Definition irq.c:56
void irq_setType(cpu_irq_t enable)
Enable specific CPU interrupt sources.
Definition irq.c:76
void irq_setTrapVector(void(*trap_vector)(void))
Set the Machine Trap Vector (mtvec).
Definition irq.c:46
@ IRQ_EXTERNAL
Definition irq.h:122
void l2cache_flush(void *address, u64 size)
Use the L2 cache registers to flush a range of memory, using physical address.
Definition l2ctrl.c:14
void l2cache_setFlushInterrupt(u64 mask)
Set L2 Cache Flush Interrupt.
Definition l2ctrl.c:27
void plic_applyConfig(plic_instance_t *inst)
Apply stored PLIC configuration to hardware.
Definition plic.c:83
RISC-V Core Interrupt Handling and Vector Table.
int irq_m_l2Cache_handler(void)
PLIC instance. Holds the software registers and hardware pointer.
Definition plic.h:137
See also
Example AXI-B Demo with L2 Cache - Learn how to use the driver with AXI-B Interface

Topics

 API Functions
 Function definitions for L2CTRL driver.
 Data Structures
 Structs and Enums used by the driver.