Default Hardware mappings for the primary Interrupt Controller and Timer.
These macros provide the base addresses and configurations for the PLIC, CLINT, and UART peripherals on the EfxSapphireSoC platform.
- The default UART is configured for 115200 baud, 8 data bits, no parity, and 1 stop bit.
- The CLINT timer is configured based on the SYSTEM_CLINT_HZ macro.
- These mappings are used by the BSP initialization and API functions to interact with the hardware peripherals.
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| #define | BSP_PLIC SYSTEM_PLIC_CTRL |
| | Primary PLIC controller base address.
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| #define | BSP_PLIC_CPU_0 SYSTEM_PLIC_CPU_0_MEI |
| | Primary PLIC CPU 0 External Interrupt base address.
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| #define | BSP_CLINT SYSTEM_CLINT_CTRL |
| | Primary CLINT controller base address.
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| #define | BSP_CLINT_HZ SYSTEM_CLINT_HZ |
| | Primary CLINT controller clock frequency.
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| #define | BSP_UART_BAUDRATE 115200 |
| | Default UART baudrate.
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| #define | BSP_UART_DATA_LEN 8 |
| | Default UART data length (bits).
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| #define | ENABLE_SEMIHOSTING_PRINT 0 |
| | Enable printing with semihosting, Disabled by default.
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| #define | BSP_UART_TERMINAL SYSTEM_UART_0_IO_CTRL |
| | Physical UART base address for standard I/O mapping.
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