RV32 SoC DS UG
High-Perf RV32 SoC DS UG
RV64 SoC DS UG API and Examples
Embedded IDE UG
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l2ctrl.c
Go to the documentation of this file.
1#include "l2ctrl/l2ctrl.h"
2
3#ifdef SYSTEM_L2_CACHE_CTRL
4#define L2CTRL ((l2ctrl_hwreg_t *)SYSTEM_L2_CACHE_CTRL)
5#else
6#define L2CTRL ((l2ctrl_hwreg_t *)0)
7#endif
8
10 while((L2CTRL->COMPLETION & 0x1U) == 0);
11 asm("fence"); // Ensure that futher reads start after the flush completion
12}
13
14void l2cache_flush(void* address, u64 size) {
15 while((L2CTRL->START & 0x1U));
16 L2CTRL->ADDRESS_FROM = (uintptr_t)address;
17 L2CTRL->ADDRESS_TO = (uintptr_t)address+size-1;
18 asm("fence");
19 L2CTRL->START = 0x3U;
20}
21
22void l2cache_flushBlocking(void* address, u64 size) {
23 l2cache_flush(address, size);
25}
26
28 L2CTRL->INTERRUPTS=mask;
29}
void l2cache_flush(void *address, u64 size)
Use the L2 cache registers to flush a range of memory, using physical address.
Definition l2ctrl.c:14
void l2cache_flushBlocking(void *address, u64 size)
Use the L2 cache registers to flush a range of memory, using physical address and wait until the flus...
Definition l2ctrl.c:22
void l2cache_setFlushInterrupt(u64 mask)
Set L2 Cache Flush Interrupt.
Definition l2ctrl.c:27
void l2cache_waitFlush()
Wait until Flush is completed.
Definition l2ctrl.c:9
#define L2CTRL
Definition l2ctrl.c:6
L2 controller driver API definitions.
uint64_t u64
Definition type.h:24