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plic.h
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1
2// Copyright (C) 2013-2026 Efinix Inc. All rights reserved.
3// Full license header bsp/efinix/EfxSapphireSocRV64/include/LICENSE.MD
5
6#ifndef PLIC_H
7#define PLIC_H
8
19
20#include "type.h"
21#include "soc.h"
22#include "riscv.h"
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
62
63/* ========================================================================== */
64/* SUB-GROUP : DATA STRUCTS */
65/* ========================================================================== */
66
90
92 typedef struct {
93 volatile u32 PRIORITY[1024];
95
97 typedef struct {
98 volatile u32 PENDING[32];
100
102 typedef struct {
103 volatile u32 ENABLE[32];
105
107 typedef struct {
108 volatile u32 THRESHOLD;
109 volatile u32 CLAIM;
110 u32 RESERVED[1022];
112
126
144 // End of PLIC_Types group
146
147/* ========================================================================== */
148/* SUB-GROUP: FUNCTIONS */
149/* ========================================================================== */
150
174 void plic_releaseExtIRQ_m(u32 gateway);
175
192
194
214
216 // End of PLIC_Funcs group
218
219#ifdef __cplusplus
220}
221#endif
222 // End of MAIN PLIC Group
224
225#endif // PLIC_H
226
void plic_releaseExtIRQ_m(u32 gateway)
Release ID source from external IRQ.
Definition plic.c:34
void plic_applyConfig(plic_instance_t *inst)
Apply stored PLIC configuration to hardware.
Definition plic.c:83
u32 plic_getThreshold(plic_instance_t *inst)
Read value from PLIC register.
Definition plic.c:68
u32 plic_getPriority(plic_instance_t *inst)
Read value from PLIC register.
Definition plic.c:45
void plic_setEnable(plic_instance_t *inst)
Set enable value to PLIC register.
Definition plic.c:50
void plic_setPriority(plic_instance_t *inst)
Set priority value to PLIC register.
Definition plic.c:40
void plic_setThreshold(plic_instance_t *inst)
Set threshold value to PLIC register.
Definition plic.c:63
u32 plic_claimExtIRQ_m()
Claim ID source from external IRQ.
Definition plic.c:28
RISC-V related functions and definitions.
Context Block: Per Target (Hart). Stride is 0x1000 (4096) bytes (Offset 0x200000).
Definition plic.h:107
u32 RESERVED[1022]
< Addressing offset: 0x04
Definition plic.h:110
volatile u32 CLAIM
< Addressing offset: 0x00
Definition plic.h:109
volatile u32 THRESHOLD
Definition plic.h:108
Enable Block: Per Target (Hart). Stride is 0x80 bytes (Offset 0x002000).
Definition plic.h:102
volatile u32 ENABLE[32]
Enables the interrupt source of each context.
Definition plic.h:103
PLIC hardware register map.
Definition plic.h:118
u32 reserved1[(0x00200000 - 0x00002400)/4U]
Address Offset: 0x2020.
Definition plic.h:123
plic_enable_block_t regs_enable[8U]
Address Offset: 0x2000.
Definition plic.h:122
plic_context_block_t regs_context[8U]
Address Offset: 0x200000.
Definition plic.h:124
u32 reserved0[0x1000U/4U-0x20U]
Address Offset: 0x1080.
Definition plic.h:121
plic_priority_block_t regs_priority
Address Offset: 0x00.
Definition plic.h:119
plic_pending_block_t regs_pending
Address Offset: 0x1000.
Definition plic.h:120
PLIC instance. Holds the software registers and hardware pointer.
Definition plic.h:137
u32 gateway
Interrupt source ID.
Definition plic.h:139
u32 target
Set Target to handler external interrupt.
Definition plic.h:138
u32 priority
Priority Level: 0=Disable, 1=Low, 3=Highest.
Definition plic.h:140
u32 enable
Interrupt Enable Bit (1=Enable).
Definition plic.h:141
u32 threshold
CPU accepts any priority > 0.
Definition plic.h:142
Pending Block: 1024 sources / 32 bits = 32 words (Offset 0x001000).
Definition plic.h:97
volatile u32 PENDING[32]
The interrupt pending status of each interrupt source.
Definition plic.h:98
Priority Block: 1024 sources max (Offset 0x000000).
Definition plic.h:92
volatile u32 PRIORITY[1024]
The interrupt priority for each interrupt source.
Definition plic.h:93
uint32_t u32
Definition type.h:26