void plic_set_priority(plic_instance_t *inst)
Set priority value to PLIC register.
u32 plic_get_threshold(plic_instance_t *inst)
Read value from PLIC register.
void plic_releaseExtIRQ_m(u32 gateway)
Release ID source from external IRQ.
void plic_applyConfig(plic_instance_t *inst)
Apply stored PLIC configuration to hardware.
u32 plic_get_priority(plic_instance_t *inst)
Read value from PLIC register.
void plic_set_threshold(plic_instance_t *inst)
Set threshold value to PLIC register.
void plic_set_enable(plic_instance_t *inst)
Set enable value to PLIC register.
u32 plic_claimExtIRQ_m()
Claim ID source from external IRQ.
RISC-V related functions and definitions.
Context Block: Per Target (Hart). Stride is 0x1000 (4096) bytes (Offset 0x200000).
u32 RESERVED[1022]
< Addressing offset: 0x04
volatile u32 CLAIM
< Addressing offset: 0x00
Enable Block: Per Target (Hart). Stride is 0x80 bytes (Offset 0x002000).
volatile u32 ENABLE[32]
Enables the interrupt source of each context.
PLIC hardware register map.
u32 reserved1[(0x00200000 - 0x00002400)/4U]
Address Offset: 0x2020.
plic_enable_block_t regs_enable[8U]
Address Offset: 0x2000.
plic_context_block_t regs_context[8U]
Address Offset: 0x200000.
u32 reserved0[0x1000U/4U-0x20U]
Address Offset: 0x1080.
plic_priority_block_t regs_priority
Address Offset: 0x00.
plic_pending_block_t regs_pending
Address Offset: 0x1000.
PLIC instance. Holds the software registers and hardware pointer.
u32 gateway
Interrupt source ID.
u32 target
Set Target to handler external interrupt.
u32 priority
Priority Level: 0=Disable, 1=Low, 3=Highest.
u32 enable
Interrupt Enable Bit (1=Enable).
u32 threshold
CPU accepts any priority > 0.
Pending Block: 1024 sources / 32 bits = 32 words (Offset 0x001000).
volatile u32 PENDING[32]
The interrupt pending status of each interrupt source.
Priority Block: 1024 sources max (Offset 0x000000).
volatile u32 PRIORITY[1024]
The interrupt priority for each interrupt source.