SG Mode Register Control Examples

Figure 1. Single-Channel in SG Mode
Table 1. Single-Channel Memory to AXI4-Stream Port in SG Mode
Step Description Related Register
1 Define the linked-list of descriptors in the memory. See Memory to AXI4-Stream Descriptor Example.
2 Set the channel input source from memory port. DMASG_CHANNEL_INPUT_CONFIG
Set bit 12 to 1.
3 Set the output of channel to AXI4-Stream port. DMASG_CHANNEL_OUTPUT_CONFIG
Set bit 12 to 0.
4 Configure the AXI4-Stream output port. DMASG_CHANNEL_OUTPUT_STREAM
For a single-channel controller, port ID is 0.
5 Set the start address of the first descriptor. DMASG_CHANNEL_LINKED_LIST_HEAD
6 Start the DMA in SG mode. DMASG_CHANNEL_STATUS
Set bit 4 to 1.
Table 2. Single-Channel AXI4-Stream to Memory Port in SG Mode
Step Description Related Register
1 Define the linked-list of descriptors in the memory. See AXI4-Stream to Memory Descriptor Example.
2 Set the input of channel from AXI4-Stream port. DMAG_CHANNEL_INPUT_CONFIG set bit 12 to 0
3 Configure the AXI4-Stream input port. DMASG_CHANNEL_INPUT_STREAM For a single-channel controller, port ID is 0.
4 Set the output of channel to memory port. DMASG_CHANNEL_OUTPUT_CONFIG
Set bit 12 to 1.
5 Set the start address of the first descriptor DMASG_CHANNEL_LINKED_LIST_HEAD
6 Start the DMA in SG mode. DMASG_CHANNEL_STATUS
Set bit 4 to 1.
Table 3. Single-Channel Memory to Memory Port in SG Mode
Step Description Related Register
1 Define the linked-list of descriptors in the memory. See Memory to Memory Descriptor Example.
2 Set the channel input source from memory port. DMASG_CHANNEL_INPUT_CONFIG
Set bit 12 to 1.
3 Set the output of channel to memory port. DMASG_CHANNEL_OUTPUT_CONFIG
Set bit 12 to 1
4 Set the start address of the first descriptor DMASG_CHANNEL_LINKED_LIST_HEAD
5 Start the DMA in SG mode. DMASG_CHANNEL_STATUS
Set bit 4 to 1.