Ports

Table 1. Clock and Reset Interfacen = Channel number.
Port Direction Description
clk Input DMA core operating clock.
reset Input Active high DMA core asynchronous reset.
ctrl_clk Input APB3 clock when APB3 interface operates in asynchronous mode.
ctrl_reset Input Active high APB3 reset when APB3 interface operates in asynchronous mode.
dat[n]_i_clk Input AXI4-stream input port clock when interface operates in asynchronous mode.
dat[n]_i_reset Input Active high AXI4-stream input port reset when interface operates in asynchronous mode.
dat[n]_o_clk Input AXI4-stream output port clock when interface operates in asynchronous mode.
dat[n]_o_reset Input Active high AXI4-stream output port reset when interface operates in asynchronous mode.
Table 2. APB3 InterfaceThe APB interface is synchronous by default. Set the IP manager parameter to change to asynchronous.
Port Direction Description
ctrl_PADDR [13:0] Input APB3 Address.
ctrl_PENABLE Input Enable port. This signal indicates the second and subsequent cycles of APB transfers.
ctrl_PSEL Input Select port. The APB bridge unit generates this signal to each peripheral bus slave. It indicates that the slave device is selected and that a data transfer is required.
ctrl_PWRITE Input Operation port.
0: APB read access
1: APB write access
ctrl_PWDATA [31:0] Input Write Data. This bus is driven by the peripheral bus bridge unit during write cycles when PWRITE is HIGH.
ctrl_PREADY Output Ready port. The slave uses this signal to extend an APB transfer.
ctrl_PRDATA [31:0] Output Read Data port. The selected slave drives this bus during read cycles when PWRITE is low.
ctrl_PSLVERROR Output This signal indicates a transfer failure but it is unused in DMA core.
Table 3. AXI4-Stream Interfacen = Channel number.
Port Direction Description
dat[n]_i_tvalid Input Indicates the master is driving a valid transfer. A transfer takes place when both dat0_i_tvalid and dat0_i_tready are asserted.
dat[n]_i_tready Output Indicates that slave port can accept a transfer.
dat[n]_i_tdata [m-1:0] Input Payload from master port.
m = Memory Interface Width
dat[n]_i_tkeep [m-1:0] Input Byte qualifier that indicates whether content of the associated byte of tdata is processed as part of the data stream.
m = Memory Interface Width
dat[n]_i_tdest [3:0] Input Routing information for the data stream.
dat[n]_i_tlast Input Indicates the boundary of a packet.
dat[n]_o_tvalid Output Indicates the master is driving a valid transfer. A transfer takes place when both tvalid and dat0_i_tready are asserted.
dat[n]_o_tready Input Indicates that a slave port can accept a transfer.
dat[n]_o_tdata [m-1:0] Output Payload to slave port.
m = Memory Interface Width
dat[n]_o_tkeep [m-1:0] Output Byte qualifier that indicates whether content of the associated byte of data is processed as part of the data stream.
m = Memory Interface Width
dat[n]_o_tdest [3:0] Output Provides routing information for the data stream.
dat[n]_o_tlast Output Indicates the boundary of a packet.
Table 4. AXI4 Interface
Ports Direction Description
write_awvalid Input Indicates that the channel is signalling a valid write address and control information.
write_awready Output Indicates that the controller is ready to accept an address and associated control signals.
write_awaddr [31:0] Input The write address gives the address of the first transfer in a write/read burst transaction.
write_awlen [7:0] Input Burst length. Indicates the exact number of transfers in a burst. Determines the number of data transfers associated with the address.
Effective burst length = io_arw_payload_len + 1
write_awsize [2:0] Input Burst size. Indicates the size of each transfer in the burst.
3b000: 1 byte
3b001: 2 bytes
3b010: 4 bytes
3b011: 8 bytes
3b100: 16 bytes
3b101: 32 bytes
3b110: 64 bytes
3b111: 128 bytes
write_awburst [1:0] Input Burst type. The burst type and the size information, determines how the address for each transfer within the burst is calculated.
2b00: fixed burst
2b01: linear burst
2b10: wrap burst
write_awlock Input Reserved.
write_awcache [3:0] Input Memory type. This signal indicates how transactions are required to progress through a system.
write_awprot [2:0] Input Protection type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.
write_awqos [3:0] Input The quality-of-service identifier.
write_region [3:0] Input Permits a single physical interface on a slave to be used for multiple logical interfaces.
write_wvalid Input Write valid. Indicates that valid write data and strobes are available.
write_wready Output Write ready. Indicates that the slave can accept the write data.
write_wdata [n-1:0] Input Write data.
n = Memory Interface Width
write_wstrb [n-1:0] Input Write strobes. Indicates which byte lanes hold valid data. There is one write strobe bit for each eight bits of the write data bus.
n = Memory Interface Width /8
write_wlast Input Write last. Indicates the last transfer in a write burst.
write_bvalid Input Write response valid. Indicates that the channel is signalling a valid write response.
write_bready Output Response ready. Indicates that the master can accept a write response.
read_arvalid Input Indicates that the channel is signalling a valid read address and control information.
read_arready Output Indicates that the controller is ready to accept an address and associated control signals.
read_araddr [31:0] Input The read address gives the address of the first transfer in a write/read burst transaction.
read_arlen [7:0] Input Burst length. Indicates the exact number of transfers in a burst. Determines the number of data transfers associated with the address.
Effective burst length = io_arw_payload_len + 1
read_arsize [2:0] Input Burst size. Indicates the size of each transfer in the burst.
3b000: 1 byte
3b001: 2 bytes
3b010: 4 bytes
3b011: 8 bytes
3b100: 16 bytes
3b101: 32 bytes
3b110: 64 bytes
3b111: 128 bytes
read_arburst [1:0] Input Burst type. The burst type and the size information, determines how the address for each transfer within the burst is calculated.
2b00: fixed burst
2b01: linear burst
2b10: wrap burst
read_arlock Input Reserved.
read_awcache [3:0] Input Memory type. This signal indicates how transactions are required to progress through a system.
read_awprot [2:0] Input Protection type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.
read_awqos [3:0] Input The quality-of-service identifier.
read_region [3:0] Input Permits a single physical interface on a slave to be used for multiple logical interfaces.
read_rvalid Output Read address valid. Indicates that the channel is signalling valid read address and control information.
read_rready Input Read ready. Indicates that the master can accept the read data and response information.
read_rdata [n-1:0] Output Read data.
n = Memory Interface Width
read_rresp [1:0] Output Read response. Indicates the status of the read transfer. This controller only responds 2b00 or OKAY.
read_rlast Output Read last. Indicates the last transfer in a read burst.

Table 5. AXI3 Interface
Port Direction Description
axi_arwvalid Input Indicates that the channel is signalling a valid write/read address and control information.
axi_arwready Output Indicates that the controller is ready to accept an address and associated control signals.
axi_arwaddr [31:0] Input The write address gives the address of the first transfer in a write/read burst transaction.
axi_arwlen [7:0] Input Burst length. Indicates the exact number of transfers in a burst. Determines the number of data transfers associated with the address.
Effective burst length = io_arw_payload_len + 1
axi_arwsize [2:0] Input Burst size. Indicates the size of each transfer in the burst.
3b000: 1 byte
3b001: 2 bytes
3b010: 4 bytes
3b011: 8 bytes
3b100: 16 bytes
3b101: 32 bytes
3b110: 64 bytes
3b111: 128 bytes
axi_arwburst [1:0] Input Burst type. The burst type and the size information, determines how the address for each transfer within the burst is calculated.
2b00: Fixed burst
2b01: Linear burst
2b10: Wrap burst
axi_arwlock Input Reserved.
axi_arwcache [3:0] Input Memory type. This signal indicates how transactions are required to progress through a system.
axi_arwprot [2:0] Input Protection type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.
axi_arwqos [3:0] Input The quality-of-service identifier.
axi_arwregion [3:0] Input Permits a single physical interface on a slave to be used for multiple logical interfaces.
axi_arwwrite Input Indicates the channel is accepting a write or read transfer.
0: Read
1: Write
axi_wvalid Input Write valid. Indicates that valid write data and strobes are available.
axi_wready Output Write ready. Indicates that the slave can accept the write data.
axi_wdata [n-1:0] Input Write data.
n = Memory Interface Width
axi_wstrb [n-1:0] Input Write strobes. Indicates which byte lanes hold valid data. There is one write strobe bit for each eight bits of the write data bus.
n = Memory Interface Width /8
axi_wlast Input Write last. Indicates the last transfer in a write burst.
axi_bvalid Input Write response valid. Indicates that the channel is signalling a valid write response.
axi_bready Output Response ready. Indicates that the master can accept a write response.
axi_rvalid Output Read address valid. Indicates that the channel is signalling valid read address and control information.
axi_rready Input Read ready. Indicates that the master can accept the read data and response information.
axi_rdata Output Read data.
n = Memory Interface Width
axi_rresp [1:0] Output Read response. Indicates the status of the read transfer. This controller only responds 2b00 or OKAY.
axi_rlast Output Read last. Indicates the last transfer in a read burst
Table 6. Conduit Interface
Port Direction Description
io_[n]_descriptorUpdate Output Outputs a pulse to indicate that the descriptor transfer is complete. This port is enabled only when parameter SG mode is enabled.
n is the channel number.
Table 7. Custom Descriptor List Interface
Port Direction Description
sg_cmd_channelId Output Indicates the DMA channel ID for request.
sg_cmd_bytesDone Output Indicates the updated status on the number of data bytes already transferred.
sg_cmd_endofPacket Output Assert high when input stream channel receives tlast to indicate the last data of the transfer.
sg_cmd_completed Output Indicates the descriptor is fully executed.
sg_cmd_valid Output Indicates the interface has new request.
sg_cmd_ready Input Indicates the descriptor logic block acknowledges the request.
sg_cmd_read Output Indicates the interface to ask for new descriptor.
sg_cmd_write Output Indicates the interface is updating the DMA state for descriptor.
sg_rsp_channelId Input Indicates the DMA channel ID for response.
sg_rsp_srcAddress Input The source address for DMA operation.
sg_rsp_dstAddress Input The destination address for DMA operation.
sg_rsp_bytes Input The total transfer bytes required for DMA operation.
sg_rsp_last Input Determine whether to assert the flag tlast to last streaming data.
sg_rsp_stall Input The DMA channel will stop and go idle if set to high.