DMA Controller Example Design

You can choose to generate the example design when generating the core in the IP Manager Configuration window. Compile the example design project and download the .hex or .bit file to your board.

Note: The Efinity IP Manager will prompt a message asking you to update the Sapphire SoC. For this example design, do not update the Sapphire SoC.
Important: Efinix tested the example design generated with the default parameter options only.
The example design settings are as shown in the following table.
Table 1. Example Design Parameter Settings
IP Manager Parameter Setting
Memory Interface Type Disable
Memory Interface External Width 64
Buffer Bank Words 1024
Buffer Bank Width 32
Buffer Bank Count 1
Memory Write Queue Disable
Memory Read Queue Disable
CSR Interface Clock Mode Enable
Custom Descriptor List Mode Enable
Priority-Weighted Round Robin Scheduler –
Channel 0 and 1 Enable Enable
Channel 0 and 1 Asynchronous Clock Mode Enable
Channel 0 and 1 SG Mode Enable
Channel 0 and 1 Circular Buffer Mode Enable
Channel 0 and 1 Channel Memory Transfer Mode Enable
Channel 0 and 1 Output Port
Channel 0: Enable
Channel 1: Disable
Channel 0 and 1 Input Port
Channel 0: Disable
Channel 1: Enable
Channel 0 and 1 Data width 32
Channel 0 and 1 Buffer Size 1024
Channel 0 and 1 Max Burst Size 128
Channel 2 and 3 Enable Enable
Channel 2 and 3 Asynchronous Clock Mode Enable
Channel 2 and 3 SG Mode Disable
Channel 2 and 3 Circular Buffer Mode Enable
Channel 2 and 3 Channel Memory Transfer Mode Disable
Channel 2 and 3 Output Port Channel 2: Enable
Channel 3: Disable
Channel 2 and 3 Input Port Channel 2: Disable
Channel 3: Enable
Channel 2 and 3 Data width 8
Channel 2 and 3 Buffer Size 1024
Channel 2 and 3 Max Burst Size 512

The example designs the target the Trion® T120 BGA576 Development Board. The example design consists of a RISC-V SoC and the DMA Controller core. The instantiated DMA Controller core has four channels, channel 0 and channel 2 with AXI4-stream output port and channel 1 with AXI4-stream input port. Each port is connected with a loopback tester which is a FIFO buffer, to fetch the data from the output of channel 0/2 to the input of channel 1/3.

Figure 1. Example Design Block Diagram
Table 2. Example Design Implementation
FPGA Logic Elements (Logic, Adders, Flipflops, etc.) Memory Blocks DSP Block fMAX (MHz)1 Efinity® Version2
System Clock DMA Clock
T120 F576 C4 23,477/112,128 (21%) 99/1056 (9%) 8/320 (3%) 86 71 2024.2
1 Using default parameter settings.
2 Using Verilog HDL.