Resource Utilization and Performance

Note: The resources and performance values provided are based on some of the supported FPGAs. These values are just guidance and may change depending on the device resource utilization, design congestion, and user design.

Table 1. Titanium Resource Utilization and Performance
FPGA	Logic Elements (Logic, Adders, Flipflops, etc.)	Memory Block	DSP Block	f_MAX (MHz)^¹	Efinity® Version^²
Ti60 F225 C4	4,002/60,800 (7%)	10/256 (4%)	0/160 (0%)	429	2024.2

Table 2. Trion® Resource Utilization and Performance
FPGA	Logic Elements (Logic, Adders, Flipflops, etc.)	Memory Blocks	DSP Block	f_MAX (MHz)^¹	Efinity® Version^²
T120 F576 C4	4,012/112,128 (4%)	14/1056 (1%)	0/320 (0%)	125	2024.2

¹ Using default parameter settings.

² Using Verilog HDL.