DMA Controller Registers

Table 1. Address MappingAll registers are 32-bit and any unlisted bits are reserved bits.
Address Offset Bit Register Description Operation
0x00 DMASG_CHANNEL_INPUT_ADDRESS
[31:0] Write source address. Write
0x08 DMASG_CHANNEL_INPUT_STREAM
[7:0] Write inputs ports to identify physical input port to use. Write
0x0C DMASG_CHANNEL_INPUT_CONFIG
0 Use to transfer to AXI4-stream port. The bit is always set to 0. Write
12 0: Transfer from AXI4-stream port
1: Transfer from memory port
13 Completion on packet. Limits the descriptor to only contain one packet and force its completion when it fully transferred into memory.
14 Wait on Packet. Ensures the channel waits for the beginning of a packet before capturing the data (avoid desync).
0x10 DMASG_CHANNEL_OUTPUT_ADDRESS
[31:0] Write the destination address. Write
0x18 DMASG_CHANNEL_OUTPUT_STREAM
[7:0] Write the outputs ports to identify the physical output port to use. Write
[15:8] Write the source port ID.
[23:16] Write the sink port ID.
0x1C DMASG_CHANNEL_OUTPUT_CONFIG
0 Transfer to AXI4-stream port. The bit is always set to 0. Write
12 0: Transfer to AXI4-stream port
1: transfer to memory port
13 Last bit. Specify end of packet to be sent at the end of a transfer.
0x20 DMASG_CHANNEL_DIRECT_BYTES
[31:0] Write the number of bytes to be transferred in direct mode. Write
0x2C DMASG_CHANNEL_STATUS
0 Set to 1 to start DMA in direct mode (also as a busy bit). Write
1 Set to 1 to start self-restart.
2 Set to 1 to set a channel to stop itself.
4 Set to 1 to start a channel using a linked-list. Ensure linked-list support is enabled by the channel.
0 1: Channel busy
0: Channel ready
 Read
0x44 DMASG_CHANNEL_PRIORITY
[2:0] Set the priority of channel 0 to 7 (7 has the highest priority). Write
[10:8] Set the weight of channel 0 to 7 (7 has the highest priority).
0x50 DMASG_CHANNEL_INTERRUPT_ENABLE
0 Enable interrupt at the end of each descriptor. Write
2 Enable interrupt when the channel is out of busy.
3 Enable interrupt when the status of descriptor is updated.
4 Enable interrupt when the channel done transferring a packet (AXI4-stream to memory).
0x54 DMASG_CHANNEL_INTERRUPT_PENDING
0 Interrupt mask status at the end of each descriptor. Read
2 Interrupt mask status when the channel is out of busy.
3 Interrupt mask status when the status of descriptor is updated.
4 Interrupt mask status when done transferring a packet (AXI4-stream to memory)
0 Clear interrupt mask at the end of each descriptor. Write
2 Clear interrupt mask when the channel is out of busy.
3 Clear interrupt mask when the status of descriptor is updated.
4 Clear interrupt mask when the channel done transferring a packet (AXI4-stream to memory).
0x60 DMASG_CHANNEL_PROGRESS_BYTES
[31:0] Read the numbers of bytes transferred for the current descriptor. This register monitors transfer progress in SG mode only. Refer to DMASG_CHANNEL_STATUS (bit 0) for Direct mode. Read
0x70 DMASG_CHANNEL_LINKED_LIST_HEAD
[31:0] Write the address of first descriptor in a linked list. Write
Table 2. Channel base Address
Channel Offset
0 0x000
1 0x080
2 0x100
3 0x180
4 0x200
5 0x280
6 0x300
7 0x380