DMA Controller Testbench

You can choose to generate the testbench when generating the core in the IP Manager Configuration window. To generate testbench, the Optional Signals option must be enabled.

Note: You must include all .v files generated in the /testbench directory in your simulation.

Important: Efinix tested the testbench generated with the default example design only.

Efinix provides a simulation script for you to run the testbench quickly using the Modelsim software. To run the Modelsim testbench script, run vsim -do modelsim.do in a terminal application. You must have Modelsim installed on your computer to use this script.

The example design includes a simulation testbench, tb_soc.v, which simulates the example design. After running the simulation, the test prints the following message:

# start dma tests ..
# proceed to memory-to-memory transfer test
# dma (32b) memory-to-memory transfer test pass!
# proceed to custom sg linked-list test
# dma (32b) custom sg linked-list transfer test pass!
# proceed to normal sg linked-list test"
# dma (32b) normal sg linked-list transfer test pass!
# proceed to direct mode test
# dma (32b) direct mode transfer test pass!
# proceed to (8b) direct mode test
# dma (8b) direct mode transfer test pass!
# TEST PASS!