Descriptor Registers

Table 1. Descriptor Register DefinitionAll descriptor registers are 32-bit write operation and any unlisted bits are reserved bits.
Address Offset Bit Register Description
0x00 Status
31 DMASG_DESCRIPTOR_STATUS_COMPLETED
Indicates that the descriptor as complete and the controller stops linked-list execution if this flag is set.
30 For AXI4-Stream to memory transfers, this bit indicates if the descriptor marks the end of a received packet.
Can be used when the bit 13 of DMASG_CHANNEL_INPUT_CONFIG_STREAM is set.
[26:0] DMASG_DESCRIPTOR_STATUS_BYTES
0x01 Control
30 For memory to AXI4-Stream transfers, indicates if an end-of-packet should be sent at the end of the transfer.
[25:0] DMASG_DESCRIPTOR_CONTROL_BYTES
Number of bytes (minus one) reserved at the descriptor FROM/TO addresses. For example, if you want to transfer 10 bytes, this field should be set to 9.
0x02 From (LSB)
[31:0] For memory to either memory or AXI4-Stream transfers, this is the memory address of the input data.
0x03 From (MSB)
[63:32] For memory to either memory or AXI4-Stream transfers, this is the memory address of the input data.
0x04 To (LSB)
[31:0] For memory or AXI4-Stream to memory transfers, this is the memory address of the output data.
0x05 To (MSB)
[63:32] For memory or AXI4-Stream to memory transfers, this is the memory address of the output data.
0x06 Next (LSB)
[31:0] Memory address of the next descriptor for execution.
0x07 Next (MSB)
[63:32] Memory address of the next descriptor for execution.