Register Map
The following tables show the PCS registers.
| Register Name | Type | Reset Value | Address Offset[7:0] |
|---|---|---|---|
| control_register | RW | 0x0031 1004 | 0x00 |
| pcsr_test_control_register | RW | 0x0000 0000 | 0x04 |
| status_register | RW | 0x0000 0000 | 0x08 |
| designcfg_register | RO | 0x0000 005F | 0x0C |
| test_seed_a_lower | RW | 0x0000 0000 | 0x10 |
| test_seed_a_upper | RW | 0x0000 0000 | 0x14 |
| test_seed_b_lower | RW | 0x0000 0000 | 0x18 |
| test_seed_b_upper | RW | 0x0000 0000 | 0x1C |
| rx_decoder_error_counter | RW | 0x0000 0000 | 0x20 |
| bit_error_counter | RW | 0x0000 0000 | 0x24 |
| test_pattern_error_counter | RW | 0x0000 0000 | 0x28 |
| prbs_error_counter | RW | 0x0000 0000 | 0x2C |
| fec_corr_error_counter | RW | 0x0000 0000 | 0x50 |
| fec_uncorr_error_counter | RW | 0x0000 0000 | 0x54 |
| interrupt_status_register | RW | 0x0000 0000 | 0x60 |
| interrupt_enable_register | RW | 0x0000 0000 | 0x64 |
| interrupt_disable_register | RW | 0x0000 0000 | 0x68 |
| interrupt_mask_register | RO | 0x0311 010A | 0x6C |
| usxgmii_link_timer_register | RW | 0x000A 3D09 | 0x70 |
| usxgmii_an_adv_register | RW | 0x0000 0000 | 0x74 |
| usxgmii_an_lp_register | RW | 0x0000 0000 | 0x78 |
| revision_register | RO | 0x0380 0100 | 0x7C |
| 10G PCS access | Value |
|---|---|
| user_apb_paddr[23:21] | 3’b110 |
| user_apb_paddr[20:11] | X (don’t care) |
| user_apb_paddr[10:8] |
3’b000: Lane 0
3’b001: Lane 1 3’b010: Lane
2 3’b011: Lane 3 |
The following tables show the bit descriptions for the PCS registers.
| Bit | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31 | usx_an_enable |
USXGMII auto-negotiation enable.
Set to 1'b1 to enable USXGMII hardware auto-negotiation state
machine.
Set to 1'b0 for non-USXGMII operation or if the application
requires software controlled negotiation.
|
RW | 0 |
| 30 | usx_an_restart |
USXGMII auto-negotiation restart.
Write 1'b1 to trigger restart of the USXGMII hardware
auto-negotiation process.
Bit 31 must also be set for auto-negotiation to function.
The hardware performs a rising-edge detect on this field,
therefore, software should always set this register field to 0 after
writing.
|
RW | 0 |
| 29:28 | usx_an_tx_type |
USXGMII auto-negotiation transmit data type.
This field is used for USXGMII software managed
auto-negotiation and is only applicable if usx_an_enable is set to
1'b0.
2'b00: Use transmit data from the MAC interface and do not
continue to monitor for new link information.
2'b01: Transmit auto-negotiation ordered sets using the value
in usx_an_adv register.
2'b10: Use transmit data from the MAC interface and continue
monitoring for new link information.
2'b11: Transmit a stream of IDLEs.
|
RW | 0 |
| 27:20 | usx_an_os_code |
USXGMII auto-negotiation ordered set code.
Set the ordered set code field to use when transmitting and
detecting auto-negotiation ordered sets.
The default value is 8'h03, which is the value defined in the
Cisco specification.
Only change the value when the RX and TX datapaths are
disabled.
|
RW | 0x03 |
| 19 | usx_an_mirror_enable |
USXGMII auto-negotiation auto mirror link info.
When set to 1'b1 and hardware auto-negotiation is enabled, the
transmitted ability values in the ACK_DET state are taken from the
received abilities from the link partner. This function applies to
all fields except for EEE capability fields.
This function is a debug feature that can be useful for MAC
devices. Do not set it for PHY devices.
|
RW | 0 |
| 18:17 | reserved | Reserved. | RO | 0 |
| 16:14 | usx_speed |
USXGMII speed. These bits and the serdes_rate field determine
the amount of replication performed to obtain the desired sub-rate.
The USXGMII speed must match the data rate of the MAC device in the
SoC.
000: 100 Mbps
001: 1 Gbps
100: 10 Gbps
Other: reserved
Only change the value when the TX and RX datapaths are
disabled.
|
RW | 0x4 |
| 13:12 | serdes_rate |
SerDes line rate. These bits control how symbols are repeated
for USXGMII operation. The following values are valid:
01: 10.3125 Gbps
Others - reserved
Only change the value when the TX and RX datapaths are
disabled.
|
RW | 0x1 |
| 11 | rx_pol_invert |
RX polarity invert. Set high to invert the incoming
RX data.
|
RW | 0 |
| 10 | tx_pol_invert | TX polarity invert. Set high to invert the TX data. | RW | 0 |
| 9 | rx_scr_bypass | RX scrambler bypass. Set high to bypass the RX descrambler.
Only change the value when the RX datapath is
disabled. |
RW | 0 |
| 8 | tx_scr_bypass | TX scrambler bypass. Set high to bypass the TX scrambler.
Only change the value when the TX datapath is
disabled. |
RW | 0 |
| 7:6 | reserved | Reserved. | RO | 0 |
| 5 | fec_err_ind |
FEC error forwarding. When high and FEC mode is enabled, upon
detection of uncorrectable errors, 66-bit blocks within the errored
FEC block are marked as errored as per the IEEE Std. 802.3 Clause 74
to ensure that affected packets to the MAC are corrupted.
The configuration option for this feature must be enabled at
compile time; when enabled it significantly increases the RX path
latency. When low, uncorrectable FEC blocks have no effect on PCS
sync headers.
Only change the value when the RX datapath is disabled.
|
RW | 0 |
| 4 | fec_enable | FEC mode enable. 1: FEC mode is enabled. 0: FEC
mode is disabled. Only change the value when the TX and
RX datapaths are disabled. |
RW | 0 |
| 3 | reserved | Reserved. | RO | 0 |
| 2 | rx_sync_reset |
RX reset.
1: Reset the receive datapath. 0: RX datapath is enabled.
|
RW | 1 |
| 1 | tx_datapath_en | TX datapath enable. Drives the tx_datapath_en signal to the TX.
1: Enable the TX datapath. 0: TX datapath is
disabled. |
RW | 0 |
| 0 | signal_ok | Enable the USXGMII/BASE-R receive PCS. Drives the signal_ok signal to the RX. If this bit is low the RX is in reset unless the post scrambler loopback mode is enabled. This bit is reset low using a hardware reset. Do not set it high until the external SerDes is supplying a suitable recovered receive clock. | RW | 0 |
| Bit | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:22 | reserved | Reserved. | RO | 0 |
| 21 | rx_prbs31_en |
Receive PRBS 31 enable. Check for PRBS 31 test pattern.
|
RW | 0 |
| 20 | rx_prbs9_en |
Receive PRBS 9 enable. Check for PRBS 9 test pattern.
|
RW | 0 |
| 19 | reserved | Reserved. | RO | 0 |
| 18 | rx_tst_dat_sel |
Receive test data select.
1: Check for pseudo random zero patterns;
0: Check for pseudo random local fault test patterns.
|
RW | 0 |
| 17 | rx_scr_idle_en |
Receive scrambled idle enable. Check for scrambled idle test
pattern.
|
RW | 0 |
| 16 | rx_tst_en |
Receive test enable. Enables receive test pattern
checking.
|
RW | 0 |
| 15:13 | reserved | Reserved. | RO | 0 |
| 12 | tx_sqw_en |
Transmit square wave enable. Set before enabling test pattern
transmission.
1: Square wave.
0: Pseudo-random.
|
RW | 0 |
| 11:10 | reserved | Reserved. | RO | 0 |
| 9 | tx_prbs31_en |
Transmit PRBS 31 enable. Selects PRBS 31 transmit test
pattern.
|
RW | 0 |
| 8 | tx_prbs9_en |
Transmit PRBS 9 enable. Selects PRBS 9 transmit test
pattern.
|
RW | 0 |
| 7 | reserved | Reserved. | RO | 0 |
| 6 | tx_tst_dat_sel |
Transmit test data select. Only used for pseudo random test
mode
1: Zero pattern sent to test generator
0: Local fault test data.
|
RW | 0 |
| 5 | tx_scr_idle_en |
Transmit scrambled idle enable. Selects scrambled idle test
pattern.
|
RW | 0 |
| 4 | tx_tst_en |
Transmit test enable. Enable transmit test pattern
transmission.
|
RW | 0 |
| 3:2 | reserved | Reserved. | RO | 0 |
| 1 | scr_lpbk_en |
TX-RX loopback at scrambler. Enables loopback at embedded
scrambler; drives scr_lpbk_en and scr_lpbk_clk_ctrl.
|
RW | 0 |
| 0 | mii_lpbk_en |
TX-RX loopback at MII. Enbles loopback at MII; drives
mii_lpbk_en and mii_lpbk_clk_ctrl.
|
RW | 0 |
| Bit | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31 | ctc_o_u_flow | CTC FIFO overflow/underflow. Indicates the internal clock tolerance compensation FIFOs have overflowed or underflowed. |
RW
W1toClr
|
0 |
| 30 | reserved | Reserved. | RO | 0 |
| 29 | hi_bit_error | Hi BER. High bit error ratio detected. |
RW
W1toClr
|
0 |
| 28 | tx_fault | TX fault. The TX encoder state machine has entered the error state. |
RW
W1toClr
|
0 |
| 27 | rx_fault | RX fault. the RX decoder state machine has entered the error state. |
RW
W1toClr
|
0 |
| 26:2 | reserved | Reserved. | RO | 0 |
| 1 | an_complete |
USXGMII auto-negotiation complete.
When the USXGMII hardware auto-negotiation feature is enabled,
this field indicates the negotiation status.
When set to 1'b1, auto-negotiation has completed and the value
received from the link partner can be obtained from
usxgmii_an_lp_register.
|
RO | 0 |
| 0 | block_lock |
Block lock. A one indicates that the
USXGMII/10GBASE-R PCS has achieved block
synchronization.
|
RO | 0 |
| Bits | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:0 | seed_a_low |
Test pattern seed A bits 31:0 for pseudo random
counter transmission.
When in PRBS mode, the scrambler seed is loaded every 128
blocks with a repeating pattern of: seed_a, seed_a_invert, seed_b,
seed_b_invert.
|
RW | 0 |
| Bit | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:26 | reserved | Reserved. | RO | 0 |
| 25:0 | seed_a_upper |
Test pattern seed A bits 57:32 for pseudo random
counter transmission.
When in PRBS mode, the scrambler seed is loaded every 128
blocks with a repeating pattern of: seed_a, seed_a_invert, seed_b,
seed_b_invert.
|
RW | 0 |
| Bit | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:0 | seed_b_low |
Test pattern seed B bits 31:0 for pseudo random
counter transmission.
When in PRBS mode, the scrambler seed is loaded every 128
blocks with a repeating pattern of: seed_a, seed_a_invert, seed_b,
seed_b_invert.
|
RW | 0 |
| Bit | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:26 | reserved | Reserved. | RO | 0 |
| 25:0 | seed_b_upper |
Test pattern seed B bits 57:32 for pseudo random
counter transmission.
When in PRBS mode, the scrambler seed is loaded every 128
blocks with a repeating pattern of: seed_a, seed_a_invert, seed_b,
seed_b_invert.
|
RW | 0 |
| Bit | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:16 | reserved | Reserved. | RO | 0 |
| 15:0 | block_error_count |
Block error count from RX decoder.
Writing any value to this register clears this field.
Due to internal clock synchronization, it may take a little
time for the clear to propagate and take effect.
|
RW
W1toClr
|
0 |
| Bit | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:16 | reserved | Reserved | RO | 0 |
| 15:0 | bit_error_count |
Bit error count from BER monitor; count of errors in the
synchronization bits. Per the IEEE Std. 802.3 specification, if
hi_ber is high, all errors may not be counted because a maximum of
16 errors can be counted in any 125 μs window for 10 Gbps.
Writing any value to this register clears this field.
Due to internal clock synchronization, it may take a little
time for the clear to propagate and take effect.
|
RW
W1toClr
|
0 |
| Bit | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:16 | reserved | Reserved. | RO | 0 |
| 15:0 | test_error_count |
Test pattern checker error count (scrambled idle
errors if rx_scr_idle_en is set and pseudo random test pattern
errors if rx_scr_idle_en is clear.
Writing any value to this register clears this field.
Due to internal clock synchronization, it may take a little
time for the clear to propagate and take effect.
|
RW
W1toClr
|
0 |
| Bit | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:16 | reserved | Reserved. | RO | 0 |
| 15:0 | prbs_rx_error_count |
PRBS RX pattern checking error count. Writing any value to this
register clears this field.
Due to internal clock synchronization, it may take a little
time for the clear to propagate and take effect.
|
RW
W1toClr
|
0 |
| Bit | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:0 | fec_block_corrected_count |
Number of FEC blocks received that were detected as errored and
were corrected.
Writing any value to this register clears this field.
Due to internal clock synchronization, it may take a little
time for the clear to propagate and take effect.
|
RW
W1toClr
|
0 |
| Bit | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:0 | fec_block_error_count |
Number of FEC blocks received that were detected as errored and
were uncorrectable. Writing any value to this register clears this
field.
Due to internal clock synchronization, it may take a little
time for the clear to propagate and take effect.
|
RW
W1toClr
|
0 |
| Bit | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:26 | reserved | Reserved. | RO | 0 |
| 25 | usxgmii_new_link_info | USXGMII new link information seen. |
RW
W1toClr
|
0 |
| 24 | usxgmii_link_sts_upd | USXGMII link status update complete. |
RW
W1toClr
|
0 |
| 23:21 | reserved | Reserved. | RO | 0 |
| 20 | fec_correctable_error | FEC correctable error occurred. |
RW
W1toClr
|
0 |
| 19:17 | reserved | Reserved. | RO | 0 |
| 16 | fec_uncorrectable_error | FEC uncorrectable error occurred. |
RW
W1toClr
|
0 |
| 15:9 | reserved | Reserved. | RO | 0 |
| 8 | block_locked | Block lock status change. |
RW
W1toClr
|
0 |
| 7:4 | reserved | Reserved. | RO | 0 |
| 3 | hi_bit_error | High bit error status triggered. |
RW
W1toClr
|
0 |
| 2 | reserved | Reserved. | RO | 0 |
| 1 | buffer_error | Elastic buffer error occurred. |
RW
W1toClr
|
0 |
| 0 | reserved | Reserved. | RO | 0 |
| Bit | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:26 | reserved | Reserved. | RO | 0 |
| 25 | usxgmii_new_link_info_en | USXGMII new link information seen enable. | WO | 0 |
| 24 | usxgmii_link_sts_upd_en | USXGMII link status update complete enable. | WO | 0 |
| 23:21 | reserved | Reserved. | RO | 0 |
| 20 | fec_correctable_error_en | FEC correctable error occurred enable. | WO | 0 |
| 19:17 | reserved | Reserved. | RO | 0 |
| 16 | fec_uncorrectable_error_en | FEC uncorrectable error occurred enable. | WO | 0 |
| 15:9 | reserved | Reserved | RO | 0 |
| 8 | block_locked_en | Block lock status change enable. | WO | 0 |
| 7:4 | reserved | Reserved. | RO | 0 |
| 3 | hi_bit_error_en | High bit error status triggered enable. | WO | 0 |
| 2 | reserved | Reserved. | RO | 0 |
| 1 | buffer_error_en | Elastic buffer error occurred enable. | WO | 0 |
| 0 | reserved | Reserved. | RO | 0 |
| Bit | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:26 | reserved | Reserved. | RO | 0 |
| 25 | usxgmii_new_link_info_dis | USXGMII new link information seen disable. | WO | 0 |
| 24 | usxgmii_link_sts_upd_dis | USXGMII link status update complete disable. | WO | 0 |
| 23:21 | reserved | Reserved. | RO | 0 |
| 20 | fec_correctable_error_dis | FEC correctable error occurred disable. | WO | 0 |
| 19:17 | reserved | Reserved. | RO | 0 |
| 16 | fec_uncorrectable_error_dis | FEC uncorrectable error occurred disable. | WO | 0 |
| 15:9 | reserved | Reserved. | RO | 0 |
| 8 | block_locked_dis | Block lock status change disable. | WO | 0 |
| 7:4 | reserved | Reserved. | RO | 0 |
| 3 | hi_bit_error_dis | High bit error status triggered disable. | WO | 0 |
| 2 | reserved | Reserved. | RO | 0 |
| 1 | buffer_error_dis | Elastic buffer error occurred disable. | WO | 0 |
| 0 | reserved | Reserved. | RO | 0 |
| Bit | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:26 | reserved | Reserved. | RO | 0 |
| 25 | usxgmii_new_link_info_mask | USXGMII new link information seen mask. | RO | 1 |
| 24 | usxgmii_link_sts_upd_mask | USXGMII link status update complete mask. | RO | 1 |
| 23:21 | reserved | Reserved. | RO | 0 |
| 20 | fec_correctable_error_mask | FEC correctable error occurred mask. | RO | 1 |
| 19:17 | reserved | Reserved. | RO | 0 |
| 16 | fec_uncorrectable_error_mask | FEC uncorrectable error occurred mask. | RO | 1 |
| 15:9 | reserved | Reserved. | RO | 0 |
| 8 | block_locked_mask | Block lock status change mask. | RO | 1 |
| 7:4 | reserved | Reserved. | RO | 0 |
| 3 | hi_bit_error_mask | High bit error status triggered mask. | RO | 1 |
| 2 | reserved | Reserved. | RO | 0 |
| 1 | buffer_error_mask | Elastic buffer error occurred mask. | RO | 1 |
| 0 | reserved | Reserved. | RO | 0 |
| Bit | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:21 | reserved | Reserved. | RO | 0 |
| 20:16 | usx_link_tim |
Link timer value to use when USXGMII hardware auto-negotiation
is enabled.
USXGMII specifies a link timer range of 1-2 ms
adjustable in steps of 0.1 ms. This register field is used with
the prescale field to determine the step granularity and the number
of steps. Set the prescale field to provide a granularity of 0.1 ms,
taking into account the SerDes link rate. Only change this
field
value when the RX datapath is disabled.
|
RW | 0x0A |
| 15:14 | reserved | Reserved. | RO | 0 |
| 13:0 | usx_link_tim_prescale |
Link timer prescaler value.
Set this field to represent 0.1 ms, taking into account the
main datapath frequency (156.25 MHz for a 10 Gbps SerDes. Multiply
this frequency by 100 to get the number of clock cycles required to
represent 0.1 ms. The default value is set for a 10 Gbps link. Only
change this field value when the RX datapath is disabled.
|
RW | 0x3D09 |
| Bit | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:16 | reserved | Reserved. | RO | 0 |
| 15:0 | usx_an_adv |
USXGMII auto-negotiation base page advertisement value.
This field's value is used when auto-negotiation ordered sets
are transmitted (hardware or software controlled).
For hardware auto-negotiation, the internal state machine
automatically sets the ACK bit if it is not already set in this
field.
Refer to the Cisco specification for more details on the valid
settings for this field.
|
RW | 0 |
| Bit | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:16 | reserved | Reserved | RO | 0 |
| 15:0 | usx_an_lp_adv |
USXGMII auto-negotiation link partner base page value.
This field's value indicates the configuration word received
from the link partner at the end of auto-negotiation when hardware
managed negotiation is enabled, or while software-managed
negotiation is in process.
|
RO | 0x0 |
| Bit | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:28 | fix_number | Fix number; incremented for fix releases. | RO | 0 |
| 27:16 | module_identification_number | PCS module identification number; fixed value. | RO | 0x380 |
| 15:0 | module_revision | Module revision. Fixed value specific to the PCS revision that is incremented for each non-fixed release. | RO | 0x0100 |