Receiver Decoder

The 64/66B decoder decodes the 66b data into 64b data and generates the associated 8b control data. The decoded data and corresponding control bits are stored as a 72b vector (64b data + 8b control).

In the decode circuit, the combinatorial decode of the encoded data happens first and is dependent on the block-type field code that is present. The output of this stage sets the start, control, terminate, error, and data signals, and also assembles the decoded data with the appropriate control block codes.

The appropriate control bit is set to a logic 1 when the octet contains a control character, or to logic 0 for a data character. Reserved characters, low power idle, and signal and sequence ordered sets (including the auto-negotiation ordered set) are also valid input data to the decoder.