Power Up Sequence

Initially, the 10GBase-KR reset controller controls the PHY_APB_RESET_N and PHY_RESET_N signals. The PHY reset signals are handed over to the client after COMMON_READY is asserted and the soft logic enters user mode. The client needs to drive the PHY reset signals high in the initial state so that the power up sequence is not impacted.

Figure 1. Power-Up Sequence
(m is 0, 1, 2, or 3)

When COMMON_READY is asserted:

  • Set PMA_XCVR_POWER_STATE_REQ to 0x0
  • Assert PMA_XCVR_PLLCLK_EN
When PMA_XCVR_PLLCLK_EN_ACK is asserted, set PMA_XCVR_POWER_STATE_REQ to A2.

There is a 100 ns (minimum) delay between the assertion of PMA_XCVR_PLLCLK_EN_ACK and when you can set PMA_XCVR_POWER_STATE_REQ to A2.

To start RX operation, the client monitors the assertion of the PHY's RX_SIGNAL_DETECT and waits for trx_cr_ceinit or trx_cr_noinit before asserting SIGNAL_OK in control_register.

Figure 2. Asserting signal_ok

Table 1. SIGNAL_OK Timing Parameters
Timing Parameters Minimum Maximum Description
trx_cr_ceinit 22.3 μs 117.4 μs Initial time required to lock clock recovery once valid data is received.
trx_cr_noinit 428 ns 593 ns Time required to lock clock recovery once valid data is received, assuming initial adaptation has been previously completed.