FEC Decoder and Block Synchronizer

If FEC mode is enabled, the 66B data blocks are passed into the FEC decoder and block synchronization module, which performs FEC framing synchronization, FEC descrambling, and FEC decoding.

The FEC decoder establishes FEC block synchronization based on repeated decoding of the 2112-bit received FEC sequence. Upon reset, the first data bit received via the gearbox is assumed to be the block start position. 2112b of data are subsequently passed through an FEC descrambling and FEC decoding circuit.

The descrambling circuit is a PN-2112 generator based on the polynomial:

g(x) = x32 + x23 + x21 + x11 + x2 + 1

From the decoding the 2112b,if the syndrome check is invalid, the block start position is shifted by one bit position and the process is repeated. Once the parity check is valid for a potential block start position, the bit slipping process is halted. If “n” consecutive FEC blocks are received with good parity then Block Sync is reported via the top level output block_lock. If any block within the “n” count fails the parity check, then the bit slipping process is restarted. Once Block Sync is established, “m” consecutive blocks with bad parity are required to drop Block Sync and restart the bit slipping mechanism.

Once FEC Block Sync has been attained, the error-correcting circuit is activated. Any subsequent FEC blocks with 11 or less consecutive bit errors are automatically corrected.

The datapath output from this module functionally matches the output of the Receive Path Synchronizer used when FEC mode is disabled.