Bit Error Ratio Monitor

The bit error ratio (BER) monitor has a 5-bit counter that counts the number of invalid sync headers detected by the normal block synchronizer or the FEC decoder. If the count reaches a certain value during a specified interval, the BER monitor sets the hi_ber register.

The monitor sets hi_ber when it detects 16 errors within a 125 μs window, and automatically writes set to the appropriate value in APB register.