Clock Tolerance Compensation

The clock tolerance compensation (CTC) module inserts or deletes IDLEs in the incoming data stream to compensate for the difference between two clocks within +/-100ppm. It can also delete the second sequence ordered set of two consecutive sequence ordered sets received from the incoming data stream.

The PCS uses a 64b datapath. However, the CTC only operates on 32b of data at a time, and only deletes or inserts 32b during a minimum IPG window (to ensure the MAC receives an IPG of at least five bytes when the PCS receives an IPG of nine bytes). A jumbo 16K frame is transmitted in approximately 2,048 cycles. 200 ppm is equivalent to a clock slip (equivalent to 64 bits) every 5,000 cycles, or a slip of 32b every 2,500 cycles, which is slightly more than the cycles needed to transmit the 16K packet. On average, expect the CTC to delete every 1.22 16K packets with a 200 ppm clock difference.

If an under/overflow condition is triggered, the CTC empties itself and recovers automatically.