PHY Clock Network
The PHY clock network is a dedicated low-skew connection from the PLLs to the HSIO2 on the left and right of the FPGA. Because the connection is very low skew, you can run the interfaces at high speed.
The PHY clock network is a dedicated low-skew connection from the PLLs to the HSIO2 on the left and right of the FPGA. Because the connection is very low skew, you can run the interfaces at high speed.