• Ti125 Data Sheet
  • Introduction
  • Features
    • Available Package Options
  • Ti125 Device Core Functional Description
    • Ti125 XLR Cell
    • Ti125 Embedded Memory
      • Ti125 True Dual-Port Mode
      • Ti125 Simple Dual-Port Mode
    • Ti125 DSP Block
    • Ti125 Clock and Control Network
      • Ti125 Clock Sources that Drive the Global and Regional Networks
      • Ti125 Driving the Global Network
      • Ti125 Driving the Regional Network
      • Ti125 Driving the Local Network
      • PHY Clock Network
      • Byte Clock Groups
  • Ti125 Device Interface Functional Description
    • Ti125 Interface Block Connectivity
    • Ti125 GPIO
      • Ti125 Features for HVIO, HSIO, and HSIO2 Configured as GPIO
        • Ti125 Double-Data I/O
        • Ti125 Programmable Delay Chains
      • Ti125 HVIO
      • Ti125 HSIO
        • Ti125 HSIO Configured as GPIO
        • Ti125 HSIO Configured as LVDS
        • Ti125 HSIO Configured as MIPI Lane
      • Ti125 HSIO2
        • Ti125 HSIO2 Configured as GPIO
        • Ti125 HSIO2 Configured as LVDS
        • Ti125 HSIO2 Configured as MIPI Lane
        • Ti125 HSIO2 Configured as QDRIO
      • I/O Banks
    • Ti125 SPI Flash Memory
    • Ti125 HyperRAM Interface
    • Ti125 Oscillator
    • Ti125 Fractional PLL
      • Ti125 Reference Clock Resource Assignments
      • Ti125 Programmable Duty Cycle
      • Ti125 Fractional Output Divider
      • Ti125 Spread-Spectrum Clocking
      • Ti125 Dynamic PLL Reconfiguration
      • Ti125 Dynamic Phase Shift
    • Ti125 Single-Event Upset Detection and Correction
    • Ti125 Internal Reconfiguration Block
  • Ti125 Security Feature
  • Ti125 Power Sequence
    • Ti125 Power-Up Sequence
    • Ti125 Power-Down Sequence
    • Ti125 Power Supply Current Transient
    • Ti125 Unused Resources and Features
  • Ti125 Configuration
    • Supported Configuration Modes
  • Ti125 Characteristics and Timing
    • Ti125 DC and Switching Characteristics
    • Ti125 HSIO and HSIO2 Electrical and Timing Specifications
    • Ti125 PLL Timing and AC Characteristics
    • Ti125 HyperRAM Characteristics
    • Ti125 Configuration Timing
      • Ti125 JTAG Mode
      • Ti125 SPI Active Mode
      • Ti125 SPI Passive Mode
  • Ti125 Pinout Description
    • Ti125 Configuration Pins
    • Ti125 Pin States
  • Ti125 Interface Floorplan
  • Ti125 Efinity Software Support
  • Ti125 Ordering Codes
  • Revision History

Ti125 Power Sequence

Important: You must follow the power-up and power-down sequence when powering Titanium FPGAs.
  • Ti125 Power-Up Sequence
  • Ti125 Power-Down Sequence
  • Ti125 Power Supply Current Transient
  • Ti125 Unused Resources and Features