Revision History

Table 1. Revision History
Date Version Description
September 2026 1.1 Byte clock group R_S0 only has 5 pairs of HSIO2 (not 6). (DOC-3058)
Updated the description for DLY_ENA, DLY_INC in Table 1. (DOC-2953)
CDI17 corrected as CDI7 in dedicated configuration pin description for SSU_N. (DOC-3074)
Updated description for differential GPIO in Table 2. (DOC-3067)
Removed incorrect instruction about turning on an external controller to the SPI flash topic. (DOC-3095)
Corrected Figure 2. (DOC-3245)
Corrected typo in Table 3; HSIO2 instead of HSIO. (DOC-3228)
Added F324 package. (DOC-3255)
Added Table 1 and Table 2.
Added SEU correction details. (DOC-3270)
April 2026 1.0 Initial release.