Ti125 Clock Sources that Drive the Global and Regional Networks

The Ti125 global and regional networks are highly flexible and configurable. Clock sources can come from interface blocks, such as GPIO or PLLs, or from the core fabric.

Table 1. Clock Sources that Drive the Global and Regional Networks
Source	Description
GPIO	Supports GCLK and RCLK. (Only the P resources support this connection type).
LVDS RX	Supports GCLK and RCLK.
MIPI RX Lane (configured as clock lane)	Supports GCLK (default) and RCLK. You can only use resources that are identified as clocks.
Clock modifiers	The byte clock group's clock modifiers have a forward clock (FWDCLK) that can drive the global and regional clock networks.
PLL	All output clocks connect to the global network. The PLL output can also drive the PHY clock network Refer to Ti125 Driving the Regional Network for the PLL clocks that drive the regional network.
Oscillator	Connects to global buffer.
Core	Signals from the core logic can drive the global or regional network.