Titanium FPGAs

Designed for compute acceleration

Sensor Aggregation
Edge Applications
Single Event Upset
Security

Titanium FPGAs for Sensor Aggregation

More and more products are using cameras and sensors these days, collecting a wealth of data. How do you aggregate and process it all? Titanium FPGAs with their powerful compute capabilities, MIPI CSI-2 and DSI support, and tiny footprint packages are here to help. Titanium FPGAs are a great solution for a variety of camera and sensor systems such as IoT, thermal cameras, industrial cameras, robotics, and smart devices.

Sensor Aggregation System

Sensor Aggregation System

The Titanium high-speed I/O (HSIO) pins support numerous single-ended and differential I/O standards. You can use them as regular GPIO or LVDS pairs. And, you can use them as MIPI RX or TX lanes running at speeds up to 1.5 Gbps. These HSIO pins are fully user configurable, so you can mix and match them to fit your system needs. Use the HSIO pins with the MIPI-CSI-2 protocol to gather data from cameras or sensors and then send it to an application processor. Or, use the DSI protocol to send imaging to a display. The Efinity® software includes a suite of D-PHY, CSI-2, and DSI IP to help you create MIPI-based systems more easily.

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Ti60 F100: Ready for Vision

Tiny Packages for Edge Applications

Video is everywhere, particularly in mobile and mobile-influenced devices like machine vision, drones, robotics, automotive, and surveillance cameras. To support innovative applications, a design needs to do more than simply take video from a camera or sensor and send it to an end processor or monitor. The video needs to be manipulated, intepreted, or analyzed near the source before it's sent off to a central data bank or processing system.

Titanium FPGAs are available in tiny packages that make it easy to add processing power to your edge system. The 3.5 x 3.4 mm 64-ball wafer-level CSP package is tiny enough to nestle right next to a sensor or camera and are very low power so they do not waste your power budget. SO you can aggregate data from one or two cameras or sensors and send the processed data to one or two displays or application processors.

The Ti60 is also available in a 100-ball package with integrated HyperRAM and SPI flash, all wrapped into a tiny 5.5 mm square package with a 0.5 mm ball pitch. Capture data from up to 3 cameras or sensors, and use the HyperRAM as a frame buffer for video, to store weights and biases for AI, to store parameters for time-of-flight (TOF) sensors, or to hold firmware for a RISC-V SoC.

Complete Camera System

Complete Camera System

Guarding against SEU

An SEU happens when an environmental factor, such as background radiation, causes a digital circuit to malfunction. For FPGAs, the most frequent (and most worrisome) outcome of an SEU is that a CRAM bit is changed from its programmed value. Designs may not use every CRAM bit in the FPGA, so an SEU may or may not cause the FPGA to malfunction. However, in many situations the safest course of action is to assume that the FPGA‘s behavior is corrupted until it is reconfigured.

Systems that Need SEU Detection

Some systems have stringent uptime requirements and/or a low error tolerance, for example, remotely deployed wireless communications systems or critical industrial applications. You can design your systems so that it can continue to operate with minimal downtime while the FPGA occasionally and randomly reconfigures itself when SEUs occur. For example, you can monitor the number of SEUs as they occur and only trigger reconfiguration when you need to.

SEU Detection Circuitry

SEU Detection Circuitry

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Titanium SEU Detection Feature

Titanium Interfaces User Guide (see Chapter 2: Device Settings)

Securing Bitstreams

By design, an FPGA can be reconfigured to perform any function you program into it. But if left undefended, a malicious user could potentially subvert the FPGA to perform some other undesired function. To be secure from this type of attack, the FPGA needs to have an anti-tampering function. One method to prevent tampering is by authenticating the configuration bitstream to ensure that the FPGA can only use the bitstream file you created. Another potential issue is intellectual property theft. After working hard to create your hardware product, the last thing you want is for someone to reverse engineer the FPGA’s functionality to steal your work and potentially create a competing product from it. To protect your IP, the FPGA needs to support bitstream encryption so you can be sure that your design is secure. Titanium FPGAs have built-in authentication and encryption security features to help keep your applications safe. You can use one or the other or both to secure your bitstream.

Authentication

Titanium FPGAs support asymmetric bitstream authentication with the RSA-4096 algorithm. You create a public/private key pair and sign the bitstream with the private key. Then, you save the public key data into fuses in the FPGA. During configuration, the FPGA validates the signature on the bitstream using the public key.

Titanium Bitstream Authentication Flow

Encryption

To ensure that your intellectual property remains safe, Titanium FPGAs use symmetric encryption with a 256-bit key and the AES-GCM-256 algorithm. You generate the key and encrypt the bitstream with it. Then, you save the key into the FPGA by blowing fuses. During configuration, the FPGA uses the stored key to decrypt the bitstream. The key cannot be extracted from the fuses, so a malicious user cannot recover the plaintext bitstream.

Titanium Bitstream Encryption Flow

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Securing Titanium Applications

Efinity Software User Guide (see Chapter 9: Configuring an FPGA > Securing Titanium Bitstreams)

Titanium FPGA Overview

You only have a few square millimeters to spare, and you need to pack in as much computing power as you can. Efinix’s next-generation Titanium FPGAs can help. Titanium FPGAs are fabricated on a 16 nm process, delivering high performance with the lowest possible power and a small physical size. They feature the innovative Quantum™ compute fabric that, with its enhanced compute capability, makes Titanium FPGAs ideal for embedded hardware acceleration applications. With a wide range of logic element (LE) densities from 35K to 1M, and compatibility with the Efinix RISC-V SoC cores, they can help you turn a tiny chip into an accelerated embedded compute system.

The Quantum compute fabric is made up of configurable tiles, the eXchangeable logic and routing (XLR) cell, that optimizes routing efficiency and speed while achieving high utilization ratios. The fabric also has highly configurable, embedded memory blocks along with dedicated, high-speed, DSP blocks. Together, these features deliver optimum performance for a wide array of applications from edge compute to industrial automation and video processing.

The 16 nm process node gives Titanium FPGAs a small footprint with low power consumption, making them ideal for highly integrated applications.

Titanium FPGA Block Diagram

Titanium FPGA Block Diagram

Ready for Computing

Titanium FPGAs are available in densities from 35K to 1 million logic elements and cover a broad range of applications:

Ti35 and Ti60

Designed for highly integrated mobile and edge devices that need low power, a small footprint, and a multitude of I/Os.

  • Mobile
  • Edge
  • AI IoT
  • Sensor fusion

Ti90, Ti120, and Ti180

Include 2.5 Gb embedded MIPI interfaces for multi-camera, high definition vision systems, edge computing and hardware acceleration.

  • Vision systems
  • Edge computing
  • Hardware acceleration
  • Machine learning

Ti240, Ti375, Ti550

Combines the compute density and transceiver interfaces for compute and industrial automation.

  • Industrial automation
  • Automotive
  • Adaptive acceleration
  • Fog computing

Ti750 and Ti1000

High-performance platform with the density and interfaces needed in the most demanding applications.

  • Communications
  • PCI Express accelerator card
  • FPGA-based server
  • Smart storage

Resource and Packaging Overview

Resources and Interfaces

Feature Ti35 Ti60 Ti90 Ti120 Ti180 Ti240 Ti375 Ti550 Ti750 Ti1000
Logic Elements (LEs) 36,176 62,016 92,534 123,379 176,256 236,888 370,137 533,174 727,056 969,408
10K RAM blocks (Mb) 1.53 2.62 6.88 9.18 13.11 19.37 27.53 39.65 54.07 72.09
DSP blocks 93 160 336 448 640 946 1,344 1,936 2,640 3,520
PLLs 4 4 10 10 10 10 10 10 10 10
GPIO 34 34 80 80 80 80 80 80 80 80
High-speed I/O 146 146 232 232 232 172 172 268 268 268
DDR4, LPDDR4 x32 x32 x32 x72 x72 2 x72 2 x72 2 x72
MIPI D-PHY 2.5 Gbps 4 RX
4 TX
4 RX
4 TX
4 RX
4 TX
3 RX
3 TX
3 RX
3 TX
3 RX
3 TX
3 RX
3 TX
3 RX
3 TX
16 Gbps Serdes x8 x8 x8 x12 x12 x16 x16 x16
25.8 Gbps Serdes x8 x8 x8
PCI Express Gen4 (16G) 1 x4 1 x4 1 x4 2 x4 2 x4 2 x8 2 x8 2 x8

Package Options

Package Pitch (mm) Size (mm) Ti35 Ti60 Ti90 Ti120 Ti180 Ti240 Ti375 Ti550 Ti750 Ti1000
64-ball WLCSP
0.4 3.5x3.4
100-ball FBGA
0.5 5.5x5.5
225-ball FBGA 0.65 10x10
361-ball FBGA 0.65 13x13
484-ball FBGA 0.65 15x15
484-ball FBGA 0.8 18x18
529-ball FBGA 0.8 19x19
625-ball FBGA 0.65 17x17
784-ball FBGA 0.8 23x23
1,156-ball FBGA 1.0 35x35

Refer to the package-dependent resources table in the FPGA data sheet for details on which resources (e.g., number of I/O, number of PLLs, or hardened interfaces) are available in each package.

Efinity Software Support

The Efinity® software provides a complete tool flow from RTL design to bitstream generation, including synthesis, place-and-route, and timing analysis. The software has a graphical user interface (GUI) that provides a visual way to set up projects, run the tool flow, and view results. The software also has a command-line flow and Tcl command console. The software-generated bitstream file configures the Titanium devices. The software supports the Verilog HDL and VHDL languages. Read more

Titanium FPGAs are fully supported by the Efinity software, which has been optimized to take full advantage of the new features of the Quantum compute fabric. The result is highly efficient synthesis and placement that delivers compact and energy efficient designs.