Titanium Ti165 FPGAs

The Ti165 FPGA features the high-density, low-power Efinix® Quantum® compute fabric wrapped with an I/O interface. This FPGA has a variety of features, such as a hardened RISC-V block, SerDes transceiver, LPDDR4/4x DRAM controller, and MIPI D-PHY.

The quad-core hardened RISC-V block has a 32-bit CPU featuring the ISA RISCV32I with M, A, C, F, and D extensions, and six pipeline stages. You utilize the hardened RISC-V block by instantiating the Sapphire High-Performance SoC, combining the speed and efficiency of a hardened RISC-V block with the flexibility of peripherals in soft logic.

The full-duplex SerDes transceiver supports multiple protocols including PCIe 4.0, Ethernet SGMII, and Ethernet 10GBase-KR protocols as well as a PMA Direct mode with data rates from 1.25 Gbps to 16 Gbps.

Ti165 FPGAs include a hardened MIPI D-PHY, which you can use with MIPI CSI-2 and DSI controller IP cores to create multi-camera, high definition vision systems, edge computing, and hardware acceleration systems. Additionally, these FPGAs have a hardened DDR DRAM controller block that supports the LPDDR4/4x DRAM interface.

  • Fabricated on a 16 nm process
  • Quad-core hardened RISC-V block
  • PCIe® Gen4 (16G)
  • 10 Gigabit Ethernet
  • High-voltage I/O (HVIO)—Simple I/O blocks that support the single-ended LVTTL and LVCMOS I/O standards.
  • High-speed I/O (HSIO)—Complex I/O blocks that support single-ended and differential I/O; LVDS, subLVDS, Mini-LVDS, and RSDS (RX, TX, and bidirectional) up to 1.6 Gbps; and also operate as MIPI lanes at 1.5 Gbps
  • MIPI D-PHY hard IP with speeds up to 2.5 Gbps
  • LPDDR4/LPDDR4x PHY (supporting x16 or x32 DQ widths) with hardened memory controller
  • Device configuration options including a standard SPI and JTAG interfaces
  • Fully supported by the Efinity® software, an RTL-to-bitstream compiler

Applications

PCIe cards, RF repeaters and radio units, small cell/massive MIMO, cable modems, machine vision, automotive, AV equipment and broadcast, medical imaging, and video bridges.

Features

Logic elements: 162800
XLR cells: 159610
10K RAM (Mb): 12.10
10K RAM (blocks): 1182
DSP Blocks: 590

Documents

Ti165 Data Sheet

Titanium Overview

Titanium Selector Guide

Find more

Available Ti165 FPGAs

Ordering
Code
Package Pins HVIO HSIO
Total
HSIO
as Pairs (1)
HSIO
as MIPI RX Lanes
Data/Clock
PLLs MIPI-DPHY DDR PCIe® Gen4 Hardened RISC-V Block SerDes Temp.
Grade
Speed
Grade
Where to Buy
Ti165C529C3 FBGA 529 51 176 88 77/11 12 x16, x32 Quad Core C 3 Find distributor
Ti165C529C3L FBGA 529 51 176 88 77/11 12 x16, x32 Quad Core C 3L Find distributor
Ti165C529C4 FBGA 529 51 176 88 77/11 12 x16, x32 Quad Core C 4 Find distributor
Ti165C529C4L FBGA 529 51 176 88 77/11 12 x16, x32 Quad Core C 4L Find distributor
Ti165C529I3 FBGA 529 51 176 88 77/11 12 x16, x32 Quad Core I 3 Find distributor
Ti165C529I3L FBGA 529 51 176 88 77/11 12 x16, x32 Quad Core I 3L Find distributor
Ti165C529I4 FBGA 529 51 176 88 77/11 12 x16, x32 Quad Core I 4 Find distributor
Ti165C529I4L FBGA 529 51 176 88 77/11 12 x16, x32 Quad Core I 4L Find distributor
1. You can use HSIO pairs as LVDS, differential HSTL, SSTL, or MIPI TX data and clock lanes.

Available Packages

C529
C529 block diagram
(19 x 19 mm, 0.8 pitch)

Dimensions and blocks shown for illustrative purposes.