SELECT `id`, `fpga`, `le`, `xlr_cells`, `ram`, `ramblock`, `mult` FROM `shop_fpga` WHERE `fpga` LIKE 'Ti60' Efinix, Inc. | Titanium Ti60 FPGA

Titanium Ti60 FPGAs

The Ti60 FPGA features the high-density, low-power 16 nm Efinix® Quantum™ fabric wrapped with an I/O interface in a small footprint package for easy integration. Ti60 FPGAs support mobile, edge, AI IoT, and sensor fusion markets that need low power, a small footprint, and a multitude of I/Os. Ti60 FPGAs:

  • Are fabricated on a 16 nm process.
  • Have high-voltage I/O (HVIO)—Simple I/O blocks that support the single-ended LVTTL and LVCMOS I/O standards.
  • Have high-speed I/O (HSIO)—Complex I/O blocks that support single-ended and differential I/O; LVDS, subLVDS, Mini-LVDS, and RSDS (RX, TX, and bidirectional) up to 1.6 Gbps; and also operate as MIPI lanes at 1.5 Gbps.
  • Have device configuration options including a standard SPI and JTAG interfaces.
  • Are fully supported by the Efinity® software, an RTL-to-bitstream compiler.

Applications

Mobile, Consumer, IoT, Edge

Features

Logic elements: 62016
XLR cells: 60800
10K RAM (Mb): 2.60
10K RAM (blocks): 256
DSP Blocks: 160

Documents

Data Sheet

Titanium Overview

Titanium Selector Guide

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Available Ti60 FPGAs

Ordering
Code
Package Pins HVIO HSIO
Total
HSIO
as Pairs (1)
HSIO
as MIPI RX Lanes
Data/Clock
PLLs Temp.
Grade
Speed
Grade
Where to Buy
Ti60W64C3 FBGA 64 0 33 17 8/2 2 C 3 DigiKey
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Ti60F100S3F2C3 FBGA 100 0 61 30 21/3 3 C 3 DigiKey
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Ti60F100S3F2C3L FBGA 100 0 61 30 21/3 3 C 3L DigiKey
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Ti60F100S3F2C4 FBGA 100 0 61 30 21/3 3 C 4 DigiKey
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Ti60F100S3F2C4L FBGA 100 0 61 30 21/3 3 C 4L DigiKey
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Ti60F100S3F2I3 FBGA 100 0 61 30 21/3 3 I 3 DigiKey
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Ti60F100S3F2I3L FBGA 100 0 61 30 21/3 3 I 3L DigiKey
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Ti60F225C3 FBGA 225 23 140 70 58/12 4 C 3 DigiKey
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Ti60F225C3L FBGA 225 23 140 70 58/12 4 C 3L DigiKey
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Ti60F225C4 FBGA 225 23 140 70 58/12 4 C 4 DigiKey
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Ti60F225C4L FBGA 225 23 140 70 58/12 4 C 4L DigiKey
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Ti60F225I3 FBGA 225 23 140 70 58/12 4 I 3 DigiKey
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Ti60F225I3L FBGA 225 23 140 70 58/12 4 I 3L DigiKey
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1. You can use HSIO pairs as LVDS, differential HSTL, SSTL, or MIPI TX data and clock lanes.

Available Packages

Ti60 FPGA
Ti60

W64
W64 block diagram
(3.5 x 3.4 mm, 0.4 pitch)

F100
F100 block diagram
(5.5 x 5.5 mm, 0.5 pitch)

F225
F225 block diagram
(8 x 8 mm, 0.5 pitch)

Dimensions and blocks shown for illustrative purposes.