UART Testbench

You can choose to generate the testbench when generating the core in the IP Manager Configuration window. To generate testbench, the Testbench Deliverables Option signals must be enabled.

Note: You must include all .v files generated in the /Testbench directory in your simulation.

Important: tested the testbench generated with the default parameter options only.

provides a simulation script for you to run the testbench quickly using the Modelsim software. To run the Modelsim testbench script, run vsim -do modelsim.do in a terminal application. You must have Modelsim installed on your computer to use this script.

The testbench performs read and write tests. Each test case indicates pass or fail for the register read/write tests.

Before running the simulation, uncomment line 19 (//'include "uart_defines.v") in the uart_demo_top.v file. After running the simulation, the test prints the following message indicating the pass/fail results:

# PASSED: Address 00000000 , DATA 5555
# PASSED: Address 00000001 , DATA aaaa
# PASSED: Address 00000002 , DATA 5555
# PASSED: Address 00000003 , DATA aaaa
# PASSED: Address 00000004 , DATA 5555
# PASSED: Address 00000005 , DATA aaaa
# PASSED: Address 00000006 , DATA 5555
# PASSED: Address 00000007 , DATA aaaa
# PASSED: Address 00000008 , DATA 5555
# PASSED: Address 00000009 , DATA aaaa
# PASSED: Address 0000000a , DATA 5555
# PASSED: Address 0000000b , DATA aaaa
# PASSED: Address 0000000c , DATA 5555
# PASSED: Address 0000000d , DATA aaaa
# PASSED: Address 0000000e , DATA 5555
# PASSED: Address 0000000f , DATA 2aaa