The UART controller consists of a UART transmitter finite state machine (FSM), UART
receiver FSM, and a baud rate generator.Figure 1. UART Controller System Block Diagram
Baud Generator
The baud generator block generates a baud tick at 16 times the baud rate. You
configure the baud generator using the BAUD parameter.
Transmitter
The transmitter block takes data from tx_data and serializes it when
tx_en is asserted. After power up, the transmitter block sends
an ASCII OK. You define the number of data bytes for the
transmitter using the BYTE parameter. If you set the transmitter to
more than 1 byte, the transmitter transfers the highest byte first.
Receiver
The receiver block contains an 8-bit receiver buffer register and a shift
register.
Figure 2. Receiver State Machine
Table 1. Receiver State Machine States
State
Description
Idle
After a reset, or after the stop or error states, the receiver
FSM resets to idle. In idle, the receiver waits for
rx_i to change from high to low. When it
detects the start bit, the FSM changes to the start state.
Start
The receiver checks whether the start bit remains low for one
bit. If it does, the receiver considers it a valid start bit. Once
it detects a valid start bit, the FSM changes to the data state.
Otherwise, it changes to the error state.
Data
The receiver waits one for one bit for each data bit to shift
into the 8-bit shift register. After the last bit is shifted In, the
FSM changes to the stop state.
Stop
The FSM waits for one bit then samples the stop bit. The receiver
does not check the stop bit length (1, 1.5, or 2 bits). After it
detects a valid stop bit, the FSM changes to the idle state.
Otherwise, it changes to the error state.
Error
The FSM sets the rx_error bit to indicate the
transmission error. The FSM changes to the idle state.
