Resource Utilization and Performance

Note: The resources and performance values provided are based on some of the supported FPGAs. These values are just guidance and may change depending on the device resource utilization, design congestion, and user design.

Table 2. Titanium Resource Utilization and Performance
FPGA	Logic and Adders	Flip-flops	Memory Blocks	DSP48 Blocks	f_MAX (MHz)^¹	Efinity® Version^²
Ti60 F225 C4	182	208	0	0	380	2022.1

Table 3. Trion Resource Utilization and Performance
FPGA	Logic Utilization (LUTs)	Registers	Memory Blocks	Multipliers	f_MAX (MHz)	Efinity® Version^²
T20 BGA256 C4	171	198	0	0	123^¹	2022.1

¹ Using default parameter settings.

² Using Verilog HDL.