Ports

Table 1. UART Core Ports
Port Interface Direction Description
clk System Input System clock.
reset System Input Synchronous active high reset.
tx_data System Input Data to transmit from the UART controller to a UART peripheral.
Configure the data width using the BYTE parameter.
baud_rate[2:0] System Input Run-time configurable baud rate.
000: 115200
001: 57600
010: 38400
011: 19200
100: 9600
101: 4800
110: 2400
111: 1200
Set the Fixed Baud Rate parameter to Disable if you want to configure the baud rate during run-time.
tx_en System Input 1: Latches the tx_data and initiates transmission.
0: No operation
tx_busy System Output
1: Data transfer in progress
0: Idle
rx_data System Output 8-bit receive data from the UART peripheral
rx_data_valid System Output
1: rx_data is valid
0: Idle
rx_error System Output A start/stop bit error was detected during the start/stop bit.
rx_parity_error System Output 1: Parity error
0: No parity error
rx_busy System Output
1: Data transfer in progress
0: Idle
baud_x16_ce System Output Enable tick from baud generator with 16 times the baud rate.
This sampling signal is useful, monitoring, debugging, and can be used to toggle the receiver operation.
tx_o Serial Output Serial data output to the communication link.
rx_i Serial Input Serial data input from the communication link.