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RV32 SoC
DS
UG
High-Perf RV32 SoC
DS
UG
RV64 SoC
DS
UG
API and Examples
Embedded IDE
UG
Sapphire RISC-V SoC Hardware Software UG
Introduction
VexRiscv RISC-V Core
Efinity RISC-V Embedded Software IDEIntroduction
Required Software
Required Hardware
Introduction
Install Software and SoC
Install the Efinity Software
Install the Efinity RISC-V Embedded Software IDE
IP Manager
Customizing the Sapphire RV64 SoC
SoC Configuration Guideline
Modify the Bootloader
Updating Bootloader with Efinity BRAM Initial Content Updater
Program the Board with the Sapphire RV64 RTL Design
About the Example Design
Installing USB Drivers
Program the Development Board
Simulate
Boot Sequence
Boot Sequence: Case A
Boot Sequence: Case B
Boot Sequence: Case C
Booting Multiple Cores
Create Your Own RTL Design
Target another FPGA
Target another Efinix Board
Target Your Own Board
Create a Custom AXI4 Master Peripheral
Create a Custom APB3 Peripheral
Use another DDR DRAM Module (Trion Only)
Use the I2C Interface for DDR Calibration (Trion only)
Remove Unused Peripherals from the RTL Design
Create Your Own Software
Deploying an Application Binary
Boot from a Flash Device
Boot from the OpenOCD Debugger
Copy a User Binary to Flash (Efinity Programmer)
About the Board Specific Package
List of BSP Files
Revision History
Revision History
Table 1.
Revision History
Date
Version
Description
May 2026
1.0
Initial release.