About the Example Design

This example targets Trion and Titanium development boards:

  • Titanium Ti375 C529 Development Board—The RTL design files are in the Ti375C529_devkit directory.
When you generate the IP core, the IP Manager creates an example design (PLL settings, SDC timing constraints, and I/O assignments) using the your chosen settings in the wizard.

The example design automatically connects UART0, SPI0, I2C0, GPIO0, the JTAG pins, and the PLL source clock pins to top-level ports, and assigns I/O pins to these peripherals once enabled. If you add more of these peripherals, you need to manually connect and create I/O assignments.

The example design uses PLL settings to look for the best effort multiplier and divider values.

Note: The following description is for the example design using the default settings.

This example design uses a simple dual-port RAM module to write to and read from the development board's memory module using the AXI interface. For the Titanium Ti375 C529 Development Board, the design uses the board's LPDDR4/LPDDR4x DRAM module.

The example design software blinks an LED and displays messages on a UART terminal.

The Sapphire RV64 SoC is configured for:
  • 200 MHz system frequency, 50 MHz peripheral frequency
  • All ISAs are enabled except Zicbom
  • All microarchitecture features are enabled
  • External memory interface is enabled with a width of 256 and a size of 1.0 GB
  • L1 data cache and instruction cache set to one way with a cache size of 4 KB
  • L2 cache set to 64 KB
  • 4 KB on-chip RAM size
  • UART 0 is enabled
  • SPI 0 is enabled
  • GPIO 0 is enabled
  • APB3 0 is enabled
  • AXI4 Slave 0 and 1 are enabled
  • AXI Master A and B are enabled

Figure 1. Example Design Block Diagram
Table 1. Example Design Implementation
FPGA Logic + Adders Flipflops Multipliers
or DSP Blocks
 Memory Blocks fMAX (MHz) Language Efinity Version
Ti375C529 42,457 35,061 17 296 204 Verilog HDL 2026.1
Note: All example designs are constrained with a 100 MHz system clock.