Booting Multiple Cores

If you configure multiple cores, the Sapphire RV64 SoC has two or more identical processors that share a common main memory and the same set of hardware I/Os. The processors can execute programs simultaneously; one processor can access the processed data or result from other processors because they are connected in a shared backplane.

With symmetric multi-processing (SMP), you can share the workload across all of the processors, resulting in less time to get a result compared to using a single-core processor. Thus, SMP helps improve overall system throughput and performance. The following flow chart explains how to do multi-core programming in a baremetal environment.

Figure 1. Boot Sequence for Multiple Cores

Table 1. SMP Helper Functions
File	Description
start.S	Functions to lock and unlock additional cores directory. To enable these functions, you should include following flag in your makefile: `CFLAGS+=-DSMP`
smpInit.S	Function to initialize the core.

These files are located in the embedded_sw/standalone/common/ directory.

Each core has a dedicated interrupt ID for the PLIC to determine which core serves the external interrupts. Refer to bsp/efinix/EfxSapphireSocRV64/include/soc.h for the interrupt ID definitions for each core:

#define SYSTEM_PLIC_CPU_0_MEI 0
#define SYSTEM_PLIC_CPU_1_MEI 1
#define SYSTEM_PLIC_CPU_2_MEI 2
#define SYSTEM_PLIC_CPU_3_MEI 3

For the Clint timer interrupt, each core has a dedicated MTIMECMP register that you can use to set the trigger. You should provide the hart ID to the API to determine which core receives the interrupt from the Clint timer. For example:

clint_setCmp(BSP_CLINT, TriggerValue, HartID);

Each core has a dedicated floating-point unit, SV39 memory management unit, physical memory protection unit, software and hardware prefetcher, and custom instruction interface, if these features are enabled in IP Manager.