Introduction

Efinix provides a configurable, cacheable soft RISC-V 64-bit SoC, that optionally includes a DDR DRAM controller interface. The Sapphire RISC-V 64-bit SoC supports a variety of peripherals. You can choose which peripherals you want by configuring the SoC in the IP Manager. This core is similar to the open-source VexiiRiscv and has been optimized for Titanium and Trion FPGAs.

Figure 1. Designing Hardware and Software for the Sapphire RV64 RISC-V SoC

The Sapphire RISC-V 64-bit SoC incorporates 1 to 4 64-bit RISC-V processors that have an instruction cache and data cache with up to 8-way (4KB per way), 64 kB to 512 kB 8-way L2 cache, 4 - 512 kB of on-chip RAM, and a variety of peripherals (including 1 - 5 APB3 slave peripherals and 2 AXI slaves and 2 AXI masters). You can configure the operating frequency from 20 to 400 MHz (the design's fMAX limits the actual performance).

Other optional CPU micro-architectures, such as like floating-point unit (FPU), dynamic branch predictor, software and hardware prefetchers, custom instruction interfaces, physical memory protection, and an SV39 memory management unit (MMU), can be configured with the IP manager.

The SoC includes a CLINT timer, a platform local interrupt controller, a watchdog timer, 1 - 5 I2C peripherals, 1 - 3 UARTs, 1 - 3 user timers, 1 - 8 user interrupts, and 1 - 3 SPI masters. The default configuration has up to a 512-bit half-duplex and full-duplex AXI bus to communicate with the Efinix LPDDR4x controller, DDR3 controller, or HyperRAM controller.

  • DDR controller—This core uses the Trion or Titanium FPGAs hard DDR DRAM interface to reset an external DRAM module (resets and reinitializes the Trion or Titanium FPGA's DDR interface, which includes the DDR module(s)).
  • HyperRAM controller—This core controls HyperRAM memory modules. You can customize the SoC using the IP Manager in the Efinity® software.