RV32 SoC DS UG
High-Perf RV32 SoC DS UG
RV64 SoC DS UG API and Examples
Embedded IDE UG
  • Efinity RISC-V Embedded Software IDE
    • Software Details
    • Toolchain
    • Installing USB Drivers
    • Install the Efinity RISC-V Embedded Software IDE
  • Launch Efinity RISC-V Embedded Software IDE
    • IDE Launcher from Efinity
    • Sapphire RV32 SoC IDE Backward Compatibility
    • Launching the Efinity RISC-V Embedded Software IDE
    • Optimization Settings
  • Create, Import, and Build a Software Project
    • Create a New Project
    • Import Sample Projects
    • Build
    • Clean and Build Project
  • Debug with the OpenOCD Debugger
    • Launch the Debug Script
      • Sapphire RV32 and RV64 SoC
      • High-Performance Sapphire RV32 SoC
    • Debug
    • Debug - Multiple Cores
      • Debug - Single Core (For Sapphire RV32 and RV64 SoC)
      • Debug - SMP
    • Debug - Daisy Chain (For Sapphire RV32 and RV64 SoC)
    • Watchpoint (For Sapphire RV64 SoC)
      • Enable Watchpoint in IP Configuration
      • Create a Watchpoint
      • Watchpoint Properties
      • Debug with Watchpoint
    • Peripheral Register View
    • CSR Register View
    • FreeRTOS View
    • QEMU Emulator
  • IDE Utilities
    • Open a Terminal
    • Enable Telnet on Windows
  • Concurrent Debugging
    • Enable Concurrent Debugging
    • Disable Concurrent Debugging
    • Concurrent SMP Debugging
    • Concurrent Debugging with Multiple Devices
    • Semihosting with Concurrent Debugging
  • Third-party Debugger
  • Troubleshooting
    • OpenOCD Error: timed out while waiting for target halted
    • Efinity Debugger Crashes when using OpenOCD
    • Non-existing file for the co_debug_register external tool
    • Error in Final Launch Sequence
    • Debug Core UUID Mismatch
    • Variable references empty selection: ${project_loc}

Debug - Multiple Cores

  • Debug - Single Core (For Sapphire RV32 and RV64 SoC)
  • Debug - SMP
Parent topic: Debug with the OpenOCD Debugger