Revision History

Table 1. Revision History
Date Document Version IP Version Description
June 2025 1.8 5.8 Add support for trigger escape command. (SIP-953)
Added [27:24] = RxTriggerEsc in mipi_debug_out[31:0] of Debug Interface table.
May 2025 1.7 5.7 Added Reset Sequence and Initialization. (DOC-2485)
Update default parameter value. (SIP-910)
Example design I/O bank update (HVIO 3.3 V). (SIP-907)
Updated example design.
Updated Customizing the MIPI DSI RX Controller.
March 2025 1.6 5.6 RTL fix for HSIO RX HS ENABLE timing. (SIP-842)
RTL fix for tHS_TRAIL improvement. (SIP-849)
January 2025 1.5 5.5 Example design update to align with MIPI Utility change (DOC-1783). (SIP-792)
December 2024 1.4 5.4 Updated mapping in Table 1 and Table 6. (DOC-2277)
December 2024 1.3 5.4 Added debug ports for internal signal observation and monitoring in Ports and Customizing the MIPI DSI RX Controller. (SIP-580)
Removed Pack Type 36 parameter from MIPI DSI RX Controller Core Parameter table. (SIP-803)
Added Testbench support.
November 2024 1.2 5.3 Added Topaz in Features and Device Support. (DOC-2102)
Added IP Version in Revision History. (DOC-2185)
Soft DPHY 1.5Gbps performance improvement. (SIP-614)
September 2024 1.1 Updated HSA value to 2. (SIP-526)
Updated Table 1, Table 1, and Table 2.
Updated Resource Utilization and Performance, IP Manager, and Example Design.
Updated pixel_data[63:0] in Figure 1.
February 2024 1.0 Initial release.