Ports

Table 1. Clock and Reset Ports
Port Direction Description
clk Input IP core clock consumed by controller logic. 100 MHz.
reset_n Input IP core reset signal.
clk_byte_HS Input MIPI RX parallel clock. This clock is a HS mode reception clock.
reset_byte_HS_n Input MIPI RX parallel clock reset signal.
clk_pixel Input Pixel clock.
reset_pixel_n Input Pixel clock reset signal.
axi_clk Input AXI4-Lite interface clock. Recommended to use the same clock as the IP core clock for the LP command to function.
axi_reset_n Input AXI4-Lite interface reset.
Table 2. MIPI RX I/O interface
Port Direction Description
Rx_LP_CLK_P Input LP mode RX clock single-ended P signal.
Rx_LP_CLK_N Input LP mode RX clock single-ended N signal.
Rx_HS_enable_C Output Signal to enable HS mode clock lane.
LVDS_termen_C Output Signal to enable HS mode clock lane termination.
Rx_LP_D_P [NUM_DATA_LANE-1:0] Input LP mode RX data single-ended P signal.
Rx_LP_D_N [NUM_DATA_LANE-1:0] Input LP mode RX data single-ended N signal.
Rx_HS_D_0[7:0] Input HS mode differential lane data bus.
Rx_HS_D_1[7:0] Input HS mode differential lane data bus.
Rx_HS_D_2[7:0] Input HS mode differential lane data bus.
Rx_HS_D_3[7:0] Input HS mode differential lane data bus.
Rx_HS_enable_D[NUM_DATA_LANE-1:0] Output Signal to enable HS mode data lane.
LVDS_termen_D[NUM_DATA_LANE-1:0] Output Signal to enable HS mode data lane termination.
fifo_rd_enable[NUM_DATA_LANE-1:0] Output RX HS mode data lane FIFO read enable signal.
fifo_rd_empty[NUM_DATA_LANE-1:0] Input RX HS mode data lane FIFO empty signal.
DLY_enable_D[NUM_DATA_LANE-1:0] Output Enable dynamic delay for Rx data lane. (Not in use for current release.)
DLY_inc_D[NUM_DATA_LANE-1:0] Output Increment dynamic delay for Rx data lane. (Not in use for current release.)
u_dly_enable_D[NUM_DATA_LANE-1:0] Input Controls the RX data lane dynamic delay. Used together with u_dly_inc_D. Refer to u_dly_inc_D for usage examples.
Available when ENABLE_USER_DESKEWCAL = 1. (Not in use for current release.)
u_dly_inc_D[NUM_DATA_LANE-1:0] Input Controls the RX data lane dynamic delay. Example: u_dly_inc_D = 1 and u_dly_enable_D =1, the delay step increases every clock cycle.
u_dly_inc_D = 0 and u_dly_enable_D = 1, the delay step decreases every clock cycle.
u_dly_enable = 0, the delay value stays put.
Available when ENABLE_USER_DESKEWCAL = 1. (Not in use for current release.)
Tx_LP_D_P Output LP mode TX data single-ended P signal.
Tx_LP_D_P_OE Output Output enable for LP mode TX data single-ended P signal.
Tx_LP_D_N Output LP mode TX data single-ended N signal.
Tx_LP_D_N_OE Output Output enable for LP mode TX data single-ended N signal.
Table 3. Video InterfaceAll signals are clocked by clk_pixel.
Port Direction Description
hsync Output Active-low horizontal sync signal.
vsync Output Active-low vertical sync signal.
pixel_data [63:0] Output Video Data. The actual data width of this port is dependent on pixel type. See Video Mode Pixel Encoding.
pixel_data_valid Output Active-high pixel data enable.
pixel_vc[1:0] Output Virtual channel signal of packet received by DSI RX controller.
pixel_format[5:0] Output Pixel data format of packet received by DSI RX controller.
Table 4. Side band InterfaceAllsignals are clocked by clk_byte_HS except irq which is clocked by axi_clk.
Port Direction Description
video_format Input Set to related video format datatype for cycle-accurate pixel interface generation when converting the decoded packets (in byte clock domain) to pixel interface (in pixel clock domain). E.g. set to 6’h3E if using RGB888 format. Tie to zeros if there is no concern for inaccuracy of pixel interface timing (especially on HSA, and HBP), then the pixel interface (hsync, vsync, pixel_data, pixel_data_valid) will be decoded based on byte clock domain.
vc[1:0] Output 2-bit virtual channel signal.
word_count[15:0] Output Byte count of the long packet received by DSI RX controller.
datatype[5:0] Output Decoded data type of packet received by DSI RX controller.
irq Output Interrupt signal for Interrupt Status Register.

Table 5. AXI4-Lite InterfaceAll signals are clocked by axi_clk.
Port Direction Description
axi_awaddr [6:0] Input AXI4-Lite write address bus.
axi_awvalid Input AXI4-Lite write address valid strobe.
axi_awready Output AXI4-Lite write address ready signal.
axi_wdata [31:0] Input AXI4-Lite write data.
axi_wvalid Input AXI4-Lite write data valid strobe.
axi_wready Output AXI4-Lite write ready signal.
axi_bvalid Output AXI4-Lite write response valid strobe.
axi_bready Input AXI4-Lite write response ready signal.
axi_araddr [6:0] Input AXI4-Lite read address bus.
axi_arvalid Input AXI4-Lite read address valid strobe.
axi_arready Output AXI4-Lite read address ready signal.
axi_rdata [31:0] Output AXI4-Lite read data.
axi_rvalid Output AXI4-Lite read data valid strobe.
axi_rready Input AXI4-Lite read data ready signal.

Table 6. Debug InterfaceAll signals are clocked with axi_clk and axi_reset_n.
Port Direction Description
mipi_debug_out[31:0] Output Debug port. Present if the parameter MIPI_DSI_RX_DEBUG is Enabled. The following is the list of internal signals that can be monitored.
[0] = pixel_fifo_full
[1] = pixel_fifo_empty
[2] = receive_error
[3] = init_done
[4] = hs_cmdfifo_full
[5] = lp_cmdfifo_full
[6] = lp_dcs_rfifo_full
[7] = hs_cmdfifo_empty
[8] = lp_cmdfifo_empty
[9] = lp_dcs_rfifo_empty
[10] = lp_cmd_in_progress
[11] = hs_crc_error
[12] = hs_ecc_1bit_error
[13] = hs_ecc_2bit_error
[14] = lp_crc_error
[15] = lp_ecc_1bit_error
[16] = lp_ecc_2bit_error
[17] = RxErrSotSyncHS_0
[18] = RxErrControl_0
[19] = RxErrEsc_0
[20] = RxStopState_0
[21] = RxSkewCalHS_0
[22] = RxUlpsActiveNot_0
[23] = RxUlpsEsc_0
[27:24] = RxTriggerEsc
[31:28] = Reserved
mipi_debug_in[31:0] Input Debug ports. Present if the parameter MIPI_DSI_RX_DEBUG is Enabled.
Currently no function has been implemented. Tie all input bits to zero.
[31:0] = reserved