Features

  • Supports 1, 2, and 4 lanes
  • Supports continuous or discontinuous clock mode
  • IP core clock frequency at 100 MHz
  • 8-bit HS mode data width
  • HS mode byte clock frequency from 10 MHz up to 187 MHz (from 80 Mbps up to 1,500 Mbps data rate)1
  • Includes AXI4-Lite interface for register access
  • Error correction code (ECC) generation for packet headers
  • Cyclic redundancy check (CRC) generation for data bytes
  • Supports non-burst with sync pulses, non-burst with sync events, and burst mode
  • Supports command transmission in HS or LP mode
  • Supports all Titanium and Topaz FPGAs
1 The maximum data rate of IP depends on the devices. Refer to the respective device data sheet for more accurate information.