Register Definition

Table 1. Control Status Registers
Word Offset Bits Name R/W Width (bits)
0x00 16:0 Interrupt status register. R/W1C 17
0x04 16:0 Interrupt enable register. R/W 17
0x08 6:0 Rx DPHY Data lane0 status. RO 7
0x0C 6:0 Rx DPHY Data lane1 status. RO 7
0x10 6:0 Rx DPHY Data lane2 status. RO 7
0x14 6:0 Rx DPHY Data lane3 status. RO 7
0x18 - 0x24 N/A Reserved. N/A N/A
0x28 1:0 Rx DPHY clock lane status. RO 2
0x2C 31:0 Received high speed write command/payload for short/long packet (hs_cmdfifo_data). RO 32
0x30 7:0 Received low power write command/payload for short/long packet (lp_cmdfifo_data). RO 8
0x34 31:0 LPDT read command data return. Write into this register to transmit the data return from peripheral (DSI RX) to host (DSI TX) (lp_dcs_rfifo_data). WO 32
0x38 23:0 ESC mode LPDT command. WO 24
0x2C - 0x40 N/A Reserved N/A N/A
0x44 15:0 Horizontal sync active (HSA) in pixel count.
Only write to this register when it is sync pulse mode.
minimum = 2
 R/W 16
0x48 15:0 Horizontal black porch (HBP) in pixel count.
For burst event mode, factor in HSA value into the HBP value (not in use as per current implemenation).
 R/W 16
0x4C 15:0 Horizontal front porch (HFP) in byte (not in use as per current implemenation). R/W 16
0x50 7:0 Vertical sync active (VSA) in line. The minimum number of lines is 1. R/W 8
0x54 7:0 Vertical black porch (VBP) in line. The minimum number of lines is 1 (not in use as per current implemenation). R/W 8
0x58 7:0 Vertical front porch (VFP) in line. The minimum number of lines is 2 (not in use as per current implemenation). R/W 8

Table 2. Interrupt Status Register Definition (0x00)
Bit Name Description
0 pixel_fifo_full Pixel FIFO full Pixel FIFO in the byte-to-pixel converter module is full.
1 pixel_fifo_empty Pixel FIFO empty Pixel FIFO in the byte-to-pixel converter module is empty.
2 undersize_pkt_error Undersize packet error. The incoming MIPI HS data byte is lesser than the wordcount value.
3 receive_error Initialization error MIPI HS data is received before tInit is completed.
4 hs_cmdfifo_full HS command fifo is full.
5 lp_cmdfifo_full LP command fifo is full.
6 lp_dcs_rfifo_full LP DCS read data fifo is full.
7 hs_cmdfifo_empty HS command fifo is empty.
8 lp_cmdfifo_empty LP command fifo is empty.
9 lp_dcs_rfifo_empty LP DCS read data fifo is empty.
10 lp_cmd_in_progress LP command transmission in LP lane is in progress.
11 hs_crc_error HS packet received CRC error indicator.
12 hs_ecc_1bit_error HS packet received ECC 1-bit error indicator.
13 hs_ecc_2bit_error HS packet received ECC 2-bit error indicator.
14 lp_crc_error LP packet received CRC error indicator.
15 lp_ecc_1bit_error LP packet received ECC 1-bit error indicator.
16 lp_ecc_2bit_error LP packet received ECC 2-bit error indicator.
Table 3. Interrupt Enable Register Definition (0x04)Each enabled interrupt status bit is aggregated to the irq output port as an indicator. By default, all interrupt enable registers are set to 1'b0 (disabled).
Bit Name Description
0 pixel_fifo_full Enable interrupt generation for pixel_fifo_full status register.
1 pixel_fifo_empty Enable interrupt generation for pixel_fifo_empty status register.
2 undersize_pkt_error Enable interrupt generation for undersize_pkt_error status register.
3 receive_error Enable interrupt generation for receive_error status register.
4 hs_cmdfifo_full Enable interrupt generation for hs_cmdfifo_full status register.
5 lp_cmdfifo_full Enable interrupt generation for lp_cmdfifo_full status register.
6 lp_dcs_rfifo_full Enable interrupt generation for lp_dcs_rfifo_full status register.
7 hs_cmdfifo_empty Enable interrupt generation for hs_cmdfifo_empty status register.
8 lp_cmdfifo_empty Enable interrupt generation for lp_cmdfifo_empty status register.
9 lp_dcs_rfifo_empty Enable interrupt generation for lp_dcs_rfifo_empty status register.
10 lp_cmd_in_progress Enable interrupt generation for LP command transmission in progress.
11 hs_crc_error Enable interrupt generation for CRC error during hs packet reception.
12 hs_ecc_1bit_error Enable interrupt generation for ECC 1-bit error during hs packet reception.
13 hs_ecc_2bit_error Enable interrupt generation for ECC 2-bit error during hs packet reception.
14 lp_crc_error Enable interrupt generation for CRC error during lp packet reception.
15 lp_ecc_1bit_error Enable interrupt generation for ECC 1-bit error during lp packet reception.
16 lp_ecc_2bit_error Enable interrupt generation for ECC 2-bit error during lp packet reception.
Table 4. D-PHY Status for Data Lanes Register Definition (0x08 – 0x24)
Bit Name Description
0 RxErrSotSyncHS Start-of-Transmission(SoT) Synchronization Error.
The core asserts this signal high for one cycle of RxWordClkHS if the HS SoT leader sequence is corrupted in a way that proper synchronization cannot be expected.
1 RxErrControl Control Error.
The core asserts this signal high when an incorrect Line state sequence is detected in LP and ALP modes. Once asserted, this signal remains asserted until the next transaction starts, so that the protocol can properly process the error.
2 RxErrEsc Escape Entry Error.
The core asserts this signal high if an unrecognized escape entry command is receivedin LP mode. Once asserted, this signal remains asserted until the next transaction starts, so that the protocol can properly process the error.
3 RxStopState Lane is in stop state.
4 Reserved Reserved.
5 RxUlpsActiveNot Ultra Low Power State (ULPS) (not) Active.
The core deasserts this signal low to indicate that the data lane is in ULP state.
6 RxUlpsEsc EscapeULPS (Receive) mode.
The core asserts this signal high to indicate that the lane module has entered the ULPS,due to the detection of a received ULPS command. The lane module remains in this mode with RxUlpsEsc asserted until a Stop state is detected on the interconnect lane.
7 Reserved Reserved.
Table 5. D-PHY Status for Clock Lane Register Definition (0x28)
Bit Name Description
0 RxUlpsActiveClkNot ULPS (not) Active.
The core asserts this signal high to indicate that the clock lane is in ULPS.
1 RxUlpsClkNot ReceiveULPS on Clock Lane.
The core deasserts this signal low to indicate that the clock lane module has entered the ULPS due to the detection of a request to enter the ULPS. The lane module remains in this mode with RxUlpsClkNot asserted until a stop state is detected on the interconnect lane.