Customizing the MIPI DSI RX Controller
The core has parameters so you can customize its function. You set the parameters in the General tab of the core's IP Configuration window.
| Name | Option | Description |
|---|---|---|
| tLPX_NS | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. The tLPX_NS
ratio between host processor and peripheral must not exceed 3:2.
The host processor is responsible for controlling its own clock
frequency to match the peripheral. The host processor LP clock
frequency must be in the range of 67% to 150% of peripheral LP
clock frequency. Default: 50 |
| tINIT_NS | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. Default:
100000 |
| tLP_EXIT_NS | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. Default: 100 |
| Bus turnaround timeout period (ns) | Values according to MIPI D-PHY specifications. | Bus turnaround timeout period in ns. Default:
100000 |
| tD_TERM_EN_NS | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. Default: 35 |
| tCLK_TERM_EN_NS | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. Default: 38 |
| tHS_PREPARE_ZERO_NS | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns (value before adding
UI). This parameter describes the expected timing
(combination of tHS_PREPARE and tHS_ZERO)
driven by transmitter from TX. Default:
145 |
| tHS_SETTLE_NS | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns (value before adding UI).
Default: 85 |
| tHS_PREPARE_NS | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns (value before adding
UI). This parameter dedicates to the transmitter timing from
RX to TX during the BTA function. Default:
40 |
| tWAKEUP_NS | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. This parameter dedicates
to the transmitter timing from RX to TX during BTA
function. Default: 1000 |
| tHS_EXIT_NS | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. This parameter dedicates
to the transmitter timing from RX to TX during BTA
function. Default: 100 |
| tHS_ZERO_NS | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns (value before adding
UI). This parameter dedicates to the transmitter timing from
RX to TX during BTA function. Default:
105 |
| tHS_TRAIL_NS | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns (value before adding
UI). This parameter dedicates to the transmitter timing from
RX to TX during BTA function. Default:
60 |
| MIPI Parallel Clock Frequency | 10 – 187 | MIPI parallel clock frequency in MHz. Round down the frequency
value to an integer if there is any floating point from your
calculation. Default: 125 |
| IP Core Clock Frequency | 40 – 100 | IP core clock frequency in MHz. Default: 100 |
| Data Lanes | 1, 2, 4 | Number of data lanes. Default: 4 |
| Enable user setting on RX data I/O lane dynamic | 0,1 | Allows user to control the RX data I/O lane dynamic delay.
Default: 0 (Not applicable anymore, always set it
to 0.) |
| DPHY Clock Mode | Continuous, Discontinuous
|
DPHY clock mode. Default: Continuous |
| Enable bidirectional DPHY | Enable, Disable | To instantiate a unidirectional or bidirectional soft
D-PHY. Default: Enable |
| Pack Type 60 | Enable, Disable | Turn on pack 60-bit datatype. For example, RGB101010.
Default: Disable |
| Pack Type 48 | Enable, Disable | Turn on pack 48-bit datatype, for example, 20-bit YCbCr, 24-bit
YCbCr, 12-bit YCbCr, RGB666 (24-bit), or RGB888. Default:
Enable |
| Pack Type 64 | Enable, Disable | Turn on pack 64-bit datatype, for example, 16-bit YCbCr or
RGB565, Default: Disable |
| Video transmission packet sequences | 0, 1, 2 | Select video mode: 0: Non-Burst Mode with Sync
Pulses 1: Non-Burst Mode with Sync event
(default) 2: Burst Mode |
| Pixel Data FIFO Depth | 256 – 8192 | FIFO depth size to store the pixel packet data (set to power of 2
value). Minimum FIFO depth required > horizontal_pixel
(HACT) x bits_per_pixel / 64 Default:
2048 |
| High-speed command write data FIFO depth | 8 – 2048 | HS command write data FIFO depth (set to power of 2
value). Default: 64 |
| Low-power write data FIFO depth | 8 – 2048 | LP command write data FIFO depth (set to power of 2
value). Default: 64 |
| Low-power read data FIFO depth | 8 – 2048 | Bus turnaround read data depth (set to power of 2
value). Default: 64 |
| MIPI_DSI_RX_DEBUG | Enable, Disable | Enable debug ports for internal signal observation and
monitoring. Default: Disable |